Study And Design Of Keccak Algorithm Fault Detection System Based On FPGA

As an important part of modern cryptography,hash functions provide the underlying encryption algorithms for many popular Internet protocols and security applications.Because of its unique structure,high security,strong performance in hardware and software,and good compatibility,the Keccak algorithm was officially adopted as new Secure Hash Algorithm(SHA-3)by the National Institute of Standards and Technology(NIST)in 2015.Considering that both the integrated circuit and the Keccak algorithm are extremely sensitive to faults,how to protect the Keccak encryption circuit from natural or man-made faults during the operation process has become one of the problems that the Keccak algorithm must solve in practical applications.Based on sufficient research of Keccak algorithm,hardware language to implement the algorithm with high performance is used.Based on the time redundancy scheme,a dual redundant code scheme fault detection scheme is designed.Compared to the structure redundancy scheme,the time redundancy scheme does not cause excessive consumption of circuit resources,but there is a disadvantage that it is impossible to detect permanent failure and the throughput is greatly reduced.In this thesis,the Dynamic Redundancy Check(DRC)is proposed to detect permanent faults,and the pipeline design reduces the overhead of time.In addition,by analyzing the cause of integrated circuit faults and its influence on the logic function of the gate circuit,a gate-level fault model is established,and a fault-error simulation system is built by using the postsim network file.Compared with most pure software simulation on algorithm node model,the system simulates more specific faults and the coverage data is more effective.The Keccak algorithm and its fault detection scheme use the tool Xillinx Vivado 2016.2 through functional simulation and complete the synthesis and implementation process on the Xilinx ISE platform.In the fault coverage simulation phase,Tcl and NcVerilog are used to build the fault simulation system.Among them,Tcl implements the function of system control and fault injection,and NcVerilog implements the function of simulating fault netlist files and responding to faults.Finally,by evaluating the results of this design on the Xilinx virtex5 FPGA,it shows that the scheme can achieve nearly 100% fault coverage with only 12.2% area and 13.4% throughput.The scheme and hardware system can provide important reference for controlling the hardware and time resource consumption of the fault detection system and improving the fault coverage.