Hardware Accelerator Design For Hash Algorithms Towards Multiple Demands

With the development of information technology, the research of information security becomes more and more important. Hash algorithm is a one-way algorithm which can be widely used in the field of digital signature, password protection and integrity checking, etc. People have different demands on the performance and areas of hardware accelerators for hash algorithm according to the different application scenarios of them. This paper proposes several different architectures of hardware accelerator for these different application scenarios.For the cases in which the area of the integrated circuit is limited, a low cost SM3 IP was designed by reusing the basic arithmetic units in a time sharing way. In addition, a SRAM was used in this architecture instead of registers to restore the intermediate variable.For the cases with high throughput requirements, a high performance SM3 IP was designed by using a two stage pipeline in the hardware architecture. In addition, the order of the operations on the critical path was reorganized so that more operations can be performed in parallel and the frequency of this IP was therefore increased.Against the weakness of existing hardware architecture for Hash algorithm that only a few algorithms are implemented, an IP which implements seven Hash algorithms including SM3, MD5, SHA-1 and SHA-2 family was designed, and the demand of a system for the diversity of the algorithm was met. By analyzing all these hash algorithms and estimating their similarity, this design reused adders and registers to the maximum extent and therefore greatly reduced the total area.