Processor Functional Verification Of Thuasdsp2004 Design And Implementation

As the semiconductor process technology steps into the deep sub-micro scale, the increasing number of transistors on single chip is making the digital system ever more complicated, and the clock frequency has already achieved the level of kilomega Hz. Additionally, the continuous growing integration level allows the smaller processor size, which results in more complex internal architecture. As progress bring more convenience to daily life, the verification and test of the processor is simultaneously becoming very difficult. Currently, the number of verification crew is usually double of the development crew in a IC develop team, the time and energy cost for verification have already taken up over half of the total, especially the verification for RTL and high level has become a bottleneck for the whole design process now. Above all, the verification for processor is undoubtedly a big challenge for the verification technology.The verification process for a digital signal processor with very long instruction word (VLIW) named THUASDSP2004, which is developed by Tsinghua University microelectronic institute sponsored by national natural science foundation, is analyzed at the register-transfer level in this paper. Besides the central processor unit (CPU), the clock generation module, memory, cache, DMA channel and peripheral devices are also included in the THUASDSP2004. This processor processes 9-stage pipeline, and RISC instruction set. Its operation frequency is capable of achieving over 150MHz. The general approach for IC test and verification and functional verification technology for processor is first discussed in this paper. Then the efforts of author in this simulation-based verification task are expatiated particularly. The work described in this paper is used to build up a simulation-based functional verification platform, which obtaining test vector via the combination of automatic pseudorandom generation and manual generation, and then verify the THUASDSP2004 by comparison between the simulation result of Verilog-HDL code and C-model of it. My main task is to generate test vector and design of an assembler. I use a published generator named...