Research And Application On The High Speed FIR Digital Filter

FIR filter is a very important part on the research and application of Digital SignalProcessing,the thesis focus on the parallel structures of high speed FIR filter design forthe demand of high speed wireless communication, with schemes analysis and parametersimulation to get specific FPGA design and implementation.Firstly，detailed elaboration of different FIR filter design principle, analysis of theirperformance and complexity is given. Secondly, to meet the proposal of800Msps,pulseshape and match filter and channel equalizers are designed respectively.Among them，Pulse shape and match filter is fixed coefficient filter,the other is variable coefficientfilter.Polyphase interpolation filter structure is selected for the design of pulse shape filter;As for match filter, time-domain and frequency-domain parallel structures are taken tocompare the parallelism and the FPGA resource consumption. The design makes use ofFIR linear phase characteristic and sliding window method to optimize FFT calculation,which could decrease70%Multiplier units. LMS algorithm, easy for hardware design, issimulated to design the high speed channel equalizer. As the feedback of LMS algorithm,so we take up the program of delayed update of FIR filter coefficients which couldimprove4times of system throughput.Through ISE timing simulation, the result shows the design of pulse shape and matchfilter, channel equalizer reaches the requirements of high speed wireless communication.The paper has a certain reference value on the design and application of FIR digital filter.