The Development Of High-Speed FPGA Board Of Preprocessing Filter For Space-borne Synthetic Aperture Radar System

The real time processing system of SAR can be divided into several relative independent stages, They are A/D transforming, range preprocessing, azimuth preprocessing, range compression, corner-turn module, azimuth compression, reverse corner-turn module. The goal of the preprocessing is overcoming the contradiction between the high processing data rate and the slow transmission data rate. In condition of keeping the quality of the imaging, we try our best to reduce the data rate for the hardware implementation of later module of the real time processing system.In this dissertation, we present our development of the Virtex-E FPGA as well as a high-speed digital signal processing board based on this FPGA. We describe our application of this FPGA board in the field of SAR signal process and find perfect results. The advantages of the FPGA board include its powerful processing ability, compact structure and high efficiency.The dissertation focuses on the design of the key component -FIR filter's design of fix coefficient. And the key of the implementation of fix coefficient FIR filter is the filter implementation in the FPGA structure. Aimed at the LUT resources in the FPGA, we choose the Distributed Arithmetic(DA) to implement FIR filter. Compared with other filter designs of preprocessing, the design based on DA prevents the Multiply-Accumulator(MAC) and improve the system's speed. It can change the filter's coefficients and taps freely because of the programmable characteristic of FPGA. The designed circuitis simple and high-speed. It meets the needs of preprocessing design.With the development of VLSI, high density memory with high speed, and computer technology, it is not very difficult to develop a full digital airborne SAR real-time signal processing system now. However, full digital, high-resolute real-time space-borne signal processing system is still a challenge. This dissertation takes the example with the design of preprocessor of space-borne real time system. Wish it help the future design of full digital space-borne real-time system of SAR.