Computer-aided Design Methods For Variational Analysis Of Nanoscale Mixed-signal Integrated Circuits

The progressively shrinking feature dimension of the latest integrated circuit (IC)technology has brought the process variation issue to the front-most scene. Process variationcauses lots of issues in IC design and manufacturing that used to be ignorable. The mainobjective of this research is to analysis the effect of process variation on integrated circuitperformance. Modern manufacturing technology makes possible massive systems-on-chip(SoC) integration, on which the most complicated structure is the on-chip interconnect system.Process variation effect has introduced variations to the resistor, capacitor and inductor valueof the interconnects, thus affecting the performance of the interconnects. On the other hand, asthe demanding for low power design is increasing, process variation effect needs to beconsidered for chip total power variation analysis. At the same time, process variation effectalso has created lots of challenges for analog integrated circuits as the variation affects thematching conditionals. This thesis is focused on solving the problems mentioned above.In order to accurately estimate the interconnect inductances under process variation, thisthesis presents a novel method for variational inductance extraction and modeling forinterconnects. The new method is based on the collocation-based spectral stochastic methodwhere orthogonal polynomials are used to represent the statistical processes. To furtherimprove the efficiency of the proposed method, a random variable reduction scheme is used.Given the interconnect wire variation parameters, the resulting method can derive theparameterized closed form of the inductance and its variation. We show that both partial andloop inductance variations can be significant given the width and height variations. Experimental results show that our method is in average350times faster than the MonteCarlo method on several practical interconnect structures.In order to solve the interconnect timing and signal integrity problems subject to processvariation, this thesis presents a novel symbolic moment calculator (SMC) for variationalinterconnect analysis. The moment calculator is constructed in a regular data structure thatincorporates binary decision diagrams (BDDs) for data storage and computation. Given aninterconnect circuit, such a computation diagram has to be constructed only once and can berepeatedly invoked for computation of moments with varying parameter values. Applicationsof the SMC for fast moment computation, statistical timing analysis, statistical signal integrityanalysis and sensitivity analysis are addressed. According to different testing cases,100to1000times speedup is demonstrated comparing to other methodology proposed in theliterature.In order to analyze full-chip total power consumption, this thesis proposes a new methodto compute the statistical total power via circuit level simulation under realistic input testingvectors. To consider the process variations with spatial correlation, we first apply weightedprinciple factor analysis method to transform the correlated variables into uncorrelated onesand meanwhile reduce the number of resulting random variables. Afterwards, Hermiteorthogonal polynomials and sparse grid techniques are used to estimate total powerdistribution in a sampling way. Experimental results show that the proposed method has100times speedup than the Monte Carlo method under fixed input vector and20times speedupthan the Monte Carlo method considering both random input vectors and process variationswith spatial correlation.In order to analyze the process variation effect for analog circuits, this thesis proposes anew performance bound analysis algorithm for analog circuits. The new method applies abinary decision diagram based symbolic analysis algorithm and affine interval arithmetic toderive the variational transfer functions of analog circuits with variational coefficients in forms of intervals. Then the frequency response bounds (maximum and minimum) areobtained by performing an analysis of a finite number of transfer functions given by theKharitonov's polynomial functions. Experimental results demonstrate90times speedup inaverage of the proposed compared to the Monte Carlo method.