Design Of The Key Modules For Digital Interphone-IF Circuit In The Receiver

With the overall progress of the wave of digitization in the field of wirelesscommunication, walkie-talkie digitization is an inevitable trend. Deficiency leads tothe high cost of digital radio in recent years，domestic and international research hasbecome a fully integrated digital the intercom receiver hair dryer dedicated chip hotchip professional digital radio. Fully integrated digital radio receiver hair dryerdedicated chip includes two parts, the front-end RF circuit and the IF circuit studydedicated chip for digital radio receiver system architecture and IF key circuit.The paper begins with an in depth analysis and comparison among three kinds ofreceiver architectures. After serious consideration and repeated simulation, Low-IFarchitecture is chosen for this work based on study of EN301166communicationprotocol. And completed the circuit of the receiver for processing the IF signal,including the IF variable gain amplifier, IF-to-Base mixer and the delta-sigmamodulator. The VGA circuits using the open-loop structure, with cascading way toachieve low power consumption, high dynamic range, and has good linearity, andinnovation to a new output common mode stabilization method eliminating the needfor separate common-mode feedback circuit, and significant savings in powerconsumption and chip area. IF-to-base mixer was a passive mixer, the ADC samplingat the same time to complete the mixing, due to the sampling of the IF signal of apassive mixer-way and4-way capacitor sharing, effectively reducing the systempower consumption and to reduce chip area, the circuit also has the ability IQmismatch caused by the mirror interference is suppressed. Improving monocyclicsecond number to quantify the structure of the low-power delta-sigma modulator,where the first stage integrator with chopper technology to improve thelow-frequency characteristics of the system, further reducing the power consumptionof the circuit, by using the low-power fully differential operational amplifier.The whole receiver is implemented using TSMC0.18μ m1P4M CMOS technique.According to the simulation, the VGA circuit and delta-sigma modulator circuitsimulation results meet the design requirements. At3V supply voltage, The VGA current consumption is504.7uA and delta-sigma modulator’s is634.5uA, to meet therequirements of low-power design. The detailed practical performance still needs tobe tested.