Research And Design Of Low Power Sigma-Delta Modulator For AI Speech Chip

With the rapid development of artificial intelligence technology,using voice commands to control equipment has become a reality.Converting voice commands into machine commands for equipment recognition needs to rely on analog-to-digital converter.Sigma-Delta analog-to-digital converter is widely used in portable speech signal processing and other fields because of its high precision and low hardware requirements.Although advanced CMOS technology can continuously reduce the power supply voltage of integrated circuits,so as to reduce power consumption,at low voltage,the distributable voltage of transistors will decrease,which will have a certain impact on the performance of the circuit.Aiming at the application field of speech recognition,this paper studies and designs the low-power Sigma-Delta modulator for AI speech chip,focusing on its low-power consumption and precision optimization.The main contents include:1.The design scheme is formulated for low-power AI voice chip and modern advanced CMOS technology.Combined with theoretical calculation,system level modeling and simulation and analysis of non ideal factors that may be introduced into the circuit,a complete design process from parameter design to circuit layout design of sigma delta modulator is summarized.2.In the aspect of improving the accuracy,the floating coefficient iteration method is used to optimize the coefficients of the modulator.After optimization,the output accuracy of the modulator can be improved by about 0.3-bit.3.In order to reduce the complexity of the sigma delta modulator circuit,the DAC feedback circuit in the modulator is studied in this paper.Different reference voltages are connected between the sampling capacitor and the sampling switch of the conventional integrator to achieve a resistance free DAC,and the circuit complexity is significantly reduced.In order to further reduce the circuit power consumption,an integrator with op amp sharing strategy is designed.The strategy redesigns the connection mode of sampling and integrating capacitors by analyzing the working states of the modulator,and uses only one integrator to complete the functions of three integrators in the third-order modulator.On this basis,combined with the idea of floating coefficient iteration,in UMC-0.11?m standard CMOS process,a low-power Sigma-Delta modulator for AI speech chip is designed,with a chip area of 0.056 mm~2.The post-simulation results show that under the 1.2 V power supply voltage and 2MHz sampling frequency,the input peak to peak differential signal is 1 V,the number of significant bits in 8 KHz speech bandwidth is 15.34-bits,and the power consumption is 104?W.Compared with the same order three integrator structure,the power consumption of the modulator is reduced by 73?W.A good balance between accuracy and power consumption is achieved by using the idea of floating coefficient iteration and the sharing strategy of operational amplifier.