Research And Design Of Sigma-delta Modulator For UHF RFID Zero-IF Receivers

Along with the continuous development of CMOS technology as well as a wide range ofapplications in the field of wireless communications, Sigma-Delta ADC adopts the technology ofover-sampling and noise shaping, and combines with the back-end digital filtering technology thenshows low sensitivity to the imperfections of its building blocks. And now it has been widely usedfor high speed and high resolution analog to digital conversion. It has extensive applications in suchfields as radio frequency receiver, digital audio, and wireless communications, etc.In this dissertation, according to the performance indicators of UHF RFID reader basebandreceiver, it researches the Sigma-Delta modulator, especially for the zero-IF receiver basebandsignal processing. First, the dissertation gives the description in detail that how based onoversampling Sigma-Delta ADC works and its variety of architectures, then analyzes the impacts ofcircuit non-idealities and noises on the performance of Sigma-Delta modulator. After that theMATLAB SIMULINK and SDToolbox has been used to do the system level design. So theparameters of each circuit block of the2ndorder Sigma-Delta modulator are confirmed. It isemphasized with the design principle and idea of each circuit blocks such as switch capacitorintegrator, gain bootstrap operational amplifiers, voltage comparators, two-phase non-overlappingclock generation circuit. Finally, the rules of the layout design are get the description in detail, thenthe layout of the system is been completed with the reasonable arrangement. In summary, all designsimulations is based on SMIC0.18μm single-poly six metal MIM CMOS process with supplyvoltage of1.8V. To achieve a2ndorder1bit modulator, fully differential switch capacitor circuitsis used in it. The simulation result shows that under64MHz sampling frequency and the Nyquistbandwidth of the input data is2MHz,53.1dB of output dynamic range is obtained with over sampleratio of32.