DFD/DFT Design And Implementation Of Pipeline Functional Unit

With the rapid promotion of the VLSI design’s frequency and the keep shrinkingof the integrated circuit manufacturing process’ feature size, the influence of manyparasitic effects on chip design is becoming noticeable, which makes the test results ofreal chip disaccord with the analytical test results before taping out, especially in somehigh performance module, the risk of inconformity is greater. Therefore, in order toreduce the risk as much as possible, by doing silicon verification of some key moduleahead of time, can ensure the chip’s functionality and performance to achieve theexpected design requirements.Pipeline functional unit is an important means to improve performance for themicroprocessor. With the microprocessor performance improved rapidly, the frequencyof pipeline functional unit is increasingly high, its internal logic is also increasinglycomplex, and the data that need to be dealt with is more and more. Besides those, theunit has lots of input and output ports, which are making its debugging and testingbecome increasingly difficult, especially more difficult to accurately locate the fault.Against the debugging and testing difficulties mentioned above, a DFD/DFT designplan for pipeline functional unit based on JTAG and LBIST is put forward. And theDFD/DFT design of the MAF unit in40nm CMOS process is also implemented.The main innovations of the thesis are as follows:1. Adopt the strategy of combining JTAG and scan design, the DFD structure ofpipeline functional unit is designed. The DFD structure is not only able to achievesingle/multi-step functional debugging and single-path functional debugging, but alsocan accurately locate the fault based on both debugging methods.2. Adopt the strategy of combining LBIST and the counter, the DFT structure ofpipeline functional unit is designed. The DFT structure is not only able to checkwhether the performance of pipeline functional unit meet the expected requirements,and debug its functionality at real speed, but also can run large amount of data to detectits functionality and performance defects and help locating the fault.3. The DFD/DFT design of pipeline functional unit has been successfully achievedin the MAF unit. The simulation results show that it is not only able to complete theexpected functionality debugging and performance testing, but also can do the faulttesting and locate the fault accurately. It is fully fit for the debugging and testingrequirements of the current pipeline functional unit. And now it has been applied to theMAF pipeline functional unit of high performance CPU in40nm CMOS process.