Research On Reconfigurable Video Coding

In the embedded system design, reconfigurable computing is more and more popular because it can use the reusable software and hardware resources to offer flexible computing ability so as to satisfy the application constraint better. Reconfigurable Video Coding (RVC) proposes a new research direction in video coding by introducing the "reconfigurable" concept into video coding field..In the traditional video coding diagram, there is only video bitstream transmitted between the sender and receiver, whereas in RVC, besides video bitstream, a kind of description information about the video bitstream is also sent to the receiver. This description information is used to help the receiver parse and decode the video bitstream and then reconfigured the final solution. Obviously, RVC owns the following advantage:The encoder and decoder is independent of video standard, thus to satisfy specific application better. The configuration is performed by parsing the description information which is more flexible. The configuration is based on video tool level other than the whole decoding perspective, which improves the tool reusability and system extensibility.RVC mainly include two parts. One is about the reconfiguration methodology, like bitstream description, derivation and parsing method about description information, dynamic reconfiguration procedure, etc. This is all about the RVC framework. The other part is about Video Tool Library (VTL), including FU description, partition granualarity, etc. MPEG and AVS both have been working on the standardization activities on RVC in the last few years. Author of this thesis participated in the RVC standardization activities. Moreover, the author also worked on the RVC implementation oriented at specific applications.In terms of RVC standard research, this dissertation focuses on the following issues.1) Methodologies to describe the variable length coding syntax elements in bitstream are proposed, including extended RVC-BSDL, separated FU, and combined RVC-BSDL and FUs. Examples are also shown to illustrate how to implement the proposed approaches in practice.2) For the VTL, an FU partition method is proposed to improve the reusability and exchangeability between FUs.3) Then, the reconfigurable architecture which can be reconfigured to support AVS is designed in the RVC simulation environment Orcc. In the reconfigurations, FUs are described in CAL which is a data-flow oriented language developed in recent years. Moreover, further discussion and exploration is carried out based on the proposed RVC architecture. Typical reconfiguration instances are shown to explore more potential abilities from RVC. Those instantiations show that RVC still leaves large space for users to explore in future. It is probable to reduce resource cost or improve performance by reconfigurations from RVC. In terms of FPGA based RVC implementation, this dissertation focuses on the following issues. Firstly, the reconfigurable architecture based on FPGA is proposed. Then the FPGA proprietary VTL which is a collection of Verilog HDL described FU is established. We mainly focus on those problems in FPGA implementation like dataflow control, FU partition and connection, FU reusability and exchangeability, on-chip data reuse. Specially, different from CAL design, the off-chip data bus design is also very important in FPGA design. We also propose efficient bus architecture in reconfiguration. Finally, FUs from VTL are invoked and connected according to the proposed methods, and entire AVS encoding solution is formed. This thesis discusses the basic issues in RVC realization, which shows that the potential of exploring parallelism dynamically at runtime for RVC is very promising.