Research On Interconnection Technology Of Functional Unit For Full-distributed VLIW Architecture

In recent years, the traditional technology promoting single-processor computing performance gradually approaches the limit, but the development of applications is on pursuit of processor performance all the time. So, many-core architecture becomes more and more concerned by researchers. The development of the current architecture design faces challenges such as line resource being expensive, high energy efficiency. To design a multi-core processor successfully, the smart core is to be devised more elaborately. And VLIW structure as a kind technology of high performance, low energy consumption, is selected by most processors. The paper selects the functional unit interconnection technology for full-distributed VLIW structure as the object of study.After in-depth study of VLIW technology, optimized interconnection of functional unit structure and associated compiler technology are proposed:1. Present design of functional unit partial interconnection. Through the data supply characteristics of media application, full interconnection network of functional unit is cut, and two kinds of partial interconnection structure of symmetric and asymmetric are put forward.2. Compiler optimization for partial interconnection is proposed. Communication scheduling is introduced into the VLIW scheduling algorithm, and heuristic rules in the operand priority and functional unit allocation are used for implementation of adaptive compilation optimization portion of the interconnect structure.3. Present design of load balancing hierarchical interconnection. On analysis of the use of registers for computationally intensive programs, the hierarchical interconnection is added to the original interconnection structure. In the design process, the idea of virtual register storage and transmission type structure of load balanced hierarchical interconnection are proposed.4. Compiler optimization for hierarchical interconnection is proposed. Through the hierarchical interconnection dispatching some heuristic rules, adapt to the compiler optimization load balanced hierarchical interconnection structure.Experiments show that, partial interconnection structure effectively reduce the area, delay and power consumption of interconnection with fair program performance, and show good scalability; hierarchical interconnection structure can ameliorate overload by registers the uneven distribution, and reduce program scheduling length within a certain range and energy consumption.