Design And Parameterized Implementation Of The Scalar Data Memory Access Unit In FT-Matrix

YHFT-Matrix DSP is a high performance32-bit floating point vector DSP used forsoftware wireless baseband, which is developed by the National University of DefenseTechnology (NUDT).The DSP uses a scalar and vector parallelization structure andalterable instruction length with16/32-bit based on VLIW technology.It supportsissuing up to10scalar and vector instructions per clock cycle.The theoretical computingperformance of this DSP can reach12GFMAC or45GMAC when the main frequency is700MHz.Designing a memory accessing unit matching with this DSP is a hugechallenge to the designers.This paper describes the design and optimization of sca lar memory accessingunit(SLS) based on the architecture of YHFT-Matrix DSP and the demand of scalaroperation.The main contents is as followings:1After analyzing the architecture of YHFT-Matrix DSP, a set of scalar dataaccessing instructions which support linear addressing mode and multi-granularity datais put forward.2According to the data accessing requirement of YHFT-Matrix DSP scalaroperation unit,this paper presents a overall design project of scalar data accessing unitand accomplishes the logic function design of the unit.The scalar data accessing unit isdivided into2parts which are scalar memory controller (SMC) and the first level datacache (L1DCache) in terms of pipeline’s function.SMC works for the whole scalaraccessing pipeline including the control of instruction decoding, address computing anddata writing back.L1DCache is duty on the cache of external scalar data.The SMC withL1DCache realizes the scalar data’s accessing of on-chip peripheral address space andexternal memory of YHFT-Matrix.3In order to reduce the accessing miss delay of L1DCache and improve theaccessing efficiency,this paper realizes three optimizing methods,which are thecombination of accessing miss,priority of loading miss and block pre-fetching.Theverification result shows that the delay of accessing miss decreased much with theexpense of5%L1DCache’s area increase.4According to the parametric design requirements of YHFT-Matrix DSP and itsoriginal system,this paper realizes a parametrized L1DCache which picks theL1DCache’s capability as design parameter.The capability of the L1DCache IP(intellectual property) soft core can be configured statically with4KB,8KB,16KB and32KB.After building a parameterized verification platform,this paper gives module-leveland system-level function verifications for SLS.The results show that the function of SLS is correct and the timing fulfils the design request.The coverage of verificationreaches more than95%with the configure of4KB,8KB,16KB or32KB. The frequencyreaches the design request of700MHz,which guarantees the well-off taped out of themulti-core chip based on YHFT-Matrix DSP IP core.