The Research And Implementation Of Key Techniques On Dynamic VLIW Architecture

Human beings have always pursued the highest performance of microprocessors. The fast development of semiconductor and manufacture techniques provides a wide space for designers. How to take full advantage of so many transistors to implement faster and more efficient microprocessors is one of the most important tasks of current computer architecture research works.Exploiting as much parallelism as possible is still the base to implement high performance computer systems. But how much parallelism can be realized depends increasingly on the inside characteristic of applications. As a fine-grained parallelism, ILP (Instruction Level Parallelism) is fundamental to implement medial-grained and coarse-grained parallelism. ILP can be exploited by either compilers or hardware mechanism. Only with reasonable division of their works in ILP oriented microarchitectures can they get satisfied performance with moderate complexity. Combining the merits of software and hardware techniques together, dynamic VLIW (Very Long Instruction Word) architecture is one of current computer architecture researching trends which have potentially high performance.To exploit more ILP in dynamic VLIW microprocessors with low hardware complexity, this paper divides the work of compilers and hardwares after studying their merits and shortcomings in detail and proposes the key issues to be resolved. This paper has following contributions:1. This paper proposes a dynamically scheduling VLIW mechanism-DLV(Deterministic Lantency Schedule for VLIW). It schedules all instructions to issue according to their deterministic latency. Reorder Buffer is employed in DLV to handle exceptions and interruptions. DLV can reduce the complexity of issue mechanism.2. Effective memory access techniques can release the gaps between processors and memory systems so that improving the performance. This paper puts forward hybrid instruction prefetching based on control flow and discusses how to perform load speculation in dynamic VLIW architectures.3. Predicated execution also brings new challenges to traditional compilers. They can only get conservative optimizations without precise predicate relation analysis. This paper proposes a new method to perform predicate analysis based on path information precisely and efficiently. It can also avoid the reconstruction of controlflow information in current predicate analysis methods.4. To exploit more ILP, compilers need to combine several basic blocks into a larger one. But it also increases the complexity of compilers. With the support of predicated execution, this paper extends HyperBlock from single entry to multiple entries and proposes corresponding optimization techniques.5. Verificating the correctness and effectivity of new techniques is one of the most important stages in computer architecture research. This paper designs and implements a prototype system based on MIPS R2000 to check the correctness and effectivity of above techniques. The prototype system provides DLV machnism and other architecture supports for compiler optimization techniques.All techniques above aim at exploiting more ILP with low hardware complexity. And they are combined in dynamic VLIW microarchitectures effectively. They can fetch up the limits of each others. Experimental results indicate that with these techniques, dynamic VLIW microprocessors can exploit more ILP and improve its performance with low complexity.