Investigation On Basic Block Scheduling Optimization For Predicate Execution VLIW DSP

The architectures of many modern high-performance digital signal processors are very long instruction word architecture and they have more instruction execution units and data storage units than conventional DSPs.The different dependencies between the before and after instructions sequence in the program is very strong.How to effectively utilize the instruction-level parallelism provided by the processor through instruction scheduling has also become a big problem.For the very long instruction word DSP that supports predicate execution,the conditional execution instruction makes the problem of instruction parallelism more complicated.Traditional methods ensure the high degree of parallelism of the code by manually writing assembly code,but this time-consuming and error-prone method has become increasingly difficult to meet the needs of very long instruction word processors.Therefore,it is very important to optimize the code scheduling at the compilation level combined with the hardware characteristics of the processor.Considering the characteristics that many instruction execution units and predicate execution of VLIW DSP processor,this paper research the basic block scheduling related problems and proposes related algorithms that help to improve the instruction parallelism.Specifically,it includes the following aspects:1.Instructions dependency analysis method of high performance DSP which supports predicate execution.DSP processors are a class of embedded systems,all of which have hardware resource configurable features,and some high-performance DSPs also have predicate execution features.In order to make full use of the hardware characteristics of the processor,this paper proposes an instructions dependency analysis method of high performance DSP which supports predicate execution.In the analysis process,the method mainly considers the dependencies between the conditional execution instructions and other instructions in the program,including the configuration dependency between the instructions.In the process of analyzing the memory access dependency and the variable dependency,the complementary condition execution instruction pair is especially considered.A more accurate direct dependency between instructions can be analyzed for a DSP processor with predicate execution characteristics2.Group heuristic instruction selection methods that estimates the function unit completion time.The VLIW DSP processor has many instruction execution units,and multiple instructions can be executed in parallel in different functional units.In order to give full play to the execution efficiency of the processor function unit,this paper propose a group heuristic instruction selection methods that estimates the function unit completion time.This method abstracts the influence of the instruction dependency on the content of the functional unit ready instruction set into the association model between functional units,and proposes two combined heuristic elements: the number of functional units with multi-level remaining instructions,and the completion time of the functional units.The method combines the number of dependent priorities of the remaining instructions in the functional unit,and predicts the time when the functional unit executes the remaining instructions during scheduling,so that the process of executing the instruction by each functional unit is more coordinated,and the execution time of the basic block code is reduced.3.Basic block merging method for low-level intermediate code.Considering the predicate execution characteristics of the high-performance DSP processor,based on the process of constructing the original control flow graph,this paper propose a basic block merging method for low-level intermediate code that can streamline the flow graph.This method mainly considers that the jump instruction in the code may be conditionally executed,and especially considers the case where a complementary condition execution jump instruction pair occurs.The basic block pairs with complementary conditional execution jump instructions and their jump target basic block pairs are merged.Since it is not necessary to consider the predicate characteristics of the processor when performing control flow analysis,the process of constructing the flow graph is simpler and clearer,and can provides a clear and effective solution for the analysis of low-level intermediate code.