| Due to the huge potential applications in military and civil fields, silicon micromechanical gyro has become the most popular research direction in MEMS field today.Therefore, the corresponding interface circuit of silicon gyroscope has also become ahot topic at home and abroad. Now, integration, digitalization, and intelligence hasbecome the focus of future research directions of silicon gyroscope, so the research ofanalog to digital conversion circuit for gyroscope has become a research priority.Therefore, for the conduct of Sigma Delta ADCs research for silicon gyro interfacecircuit has a very important significance and application prospects.According to the characteristics of the interface circuit of silicon gyroscope, thistopic briefly introduces the working principle of Sigma Delta ADC. Based on therequirements of the modulator design, Sigma Delta modulator structures are carefullyanalyzed and also carried on the comparison and optimization. Hereby, a three orderthree bits quantization in single-loop with partial feedback of feed-forward summationsystem structure for modulator is designed in this paper, and then the ideal model ofmodulator system in Matlab is simulated. In addition, the focus of this topic is mainlyon the nonlinear factors analysis and modeling, and the Data Weighted Average (DWA)technique used in multi-bit quantization is introduced as well as modeling in systemlevel. Then, the non-ideal modeling of system is simulated in Matlab. Based on thedesign of the system level model, the full differential modulator in circuit level isdesigned, and also the design of each module circuit is completed and transistor level iscarried out in Cadence for circuit simulation.In system level design, this paper adopts feed-forward summation and multi-bitquantization structure to reduce the output of the integrator, increase the noiseperformance of the modulator, and make it easier for the system stability. Furthermore,the use of partial feedback in the structure for zero-point optimization improves thenoise shaping ability in signal bandwidth of modulator. This topic employs thesingle-loop third-order three-bit quantization structure, and the sampling rate is64,signal bandwidth is200KHz, and the sampling clock frequency is25.6MHz. Throughthe simulation in the Simulink, the Signal-to-Noise Ratio (SNR) for the ideal modeling is125dB, and the Effective Number of Bits (ENOB) is20.48. Via the established modelof modulator’s nonlinear factors, the nonlinear systems Simulink simulation resultsobtained SNR of104dB, and the ENOB is16.98.In order to reduce the harmonic distortion of the modulator, transistor level isimplemented by fully-differential switch capacitor circuit. The structure at all levels ofthe integrator was optimized. To reduce the influence of flicker noise, the integratoradopts Correlated Double Sampling (CDS) technology, and the partial feedback circuitdesign is improved. The fully-differential operational amplifier with high slew-rate andhigh bandwidth is designed, and uses switch capacitor circuit as common-modefeedback. Dynamic comparator and multi-bit quantizer are designed to improve thespeed of the quantizer and reduce power consumption. The design the nonlinearcompensation feedback DAC module--DWA module circuit--realizes noise shaping ofcapacitance matching error. The overall circuit was simulated in Cadence by0.5umprocess. Transistor-level simulation result shows that the SNR is101.3dB, and theeffective number of bits is16.54bits. The simulation results are consistent with theestablished non-ideal model of modulator, which verifies the correction of system leveldesign method. |
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