Design And Verification Of The Digital Modulator In16Bit Sigma-delta DAC

Nowadays, as the digital integrated circuit technology of Micro-Electro-Mechanical Systems sensor has digital anti-interference ability, high reliability, highperformance, large-scale integration and other advantages, digital integration of MEMSgyroscope’s interface circuit has become one of the hottest trends in the development ofMEMS gyroscope. Therefore, the study of high-performance ADCs and DACs used inthe interface circuit of gyroscope is very important. Compared to the traditional DAC,Sigma-Delta DAC can achieve higher precision, so it has a very important significancefor enhancing the overall performance of digital MEMS gyroscope.This subject comes from MEMS Center of Harbin Institute of Technology aboutthe research of digital gyroscope’s ASIC integrated solutions. According to briefintroduction of Sigma-Delta DAC system architecture, the oversampling technique andnoise shaping technique of Sigma-Delta modulation are analyzed in depth. Hence aSigma-Delta digital modulator with third order4-bit quantization, using a single loopcascaded integrator distributed feed-forward structure is designed in this paper. Takelocal feedback technology to optimize the zero of noise transfer function, optimize thecoefficients with CSD code and analysis stability of the system. Then use the MatlabSimulink platform to build the system model of digital modulator. The signal bandwidthis100KHz, the oversampling ratio is64and the sampling clock frequency is12.8MHz.Simulation results show that the SNDR can reach120.3dB, ENOB is19.7. Conclusivelythe RTL level of Sigma-Delta digital modulator is implemented, and functionalsimulation is completed by Modelsim software. Compare with system-level simulationresults, it verifys the validity of the RTL model.Due to the multi-bit quantization in Sigma-Delta modulator, mismatch error isgenerated. This paper uses Data Weighted Average (DWA) algorithm for its mismatchnoise shaping to reduce the nonlinearity error caused by the mismatch. However, as theinput signal is DC or low frequency periodic for DWA algorithm, it will induce tonesaliased to the Sigma-Delta modulator baseband. For this reason, by increasing thenumber of unit DACs to improve DWA algorithm, and its system model and simulationare accomplished. Finally, prove that the system model of IDWA-DAC is valid, and iteffectively improves the dynamic range.Digital synthesis and implementation of Sigma-Delta modulator are finished. TheFPGA verification results show that the second harmonic at-145.3dB, third harmonic at-135.9dB, the maximum signal to noise ratio can reach120.73dB, effective number ofbits is19, to meet the design requirements completely.