The Design Of Multibit Sigma-Delta ADC

With the demand of digitalize and intelligentize of MEMS gyroscope, the research for digital gyroscope interface has become a hot topic, especially focus on the design of analog-to-digital converter and digital-to-analog converter. The thesis introduces the construction and performance specification of Sigma-Delta ADC. The rationale of Sigma-Delta modulator was also elaborate too. Advantages comparison between single-bit and multi-bit quantization was presented. According to the designing requirements, three-order 3-bit quantization full-forward Sigma-Delta modulator was selected. Non-idea factors were analyzed and modeled based on Simulink. Finally transistor level Sigma-Delta modulator was simulation, and its simulation results was analyzed.Sigma-Delta modulator system was designed in Simulink of Matlab. System SNR is 125.4d B, and ENOB is 20.53 bits on 10 MHz sampling frequency, 128 over-sampling without considering non-idealities. System non-idealities were mainly focused on integrator setting error, finite gain and bandwidth of op-amp, non-linearity of CMOS switch, KT/C and op-amp noise, these non-idealities were analyzed and modeled in Simulink. Non-linearity led by Feedback DAC capacitor mismatch was also considered. DWA and IDWA Simulink model download from mathwork were adopted to verify non-linearity suppression. After considering non-idealities analyzed before and 1% feedback capacitor mismatch, the 3rd harmonic distortion smaller than-100 d B and ENOB is 16 bits which satisfies the design requirement.First stage integrator needs to be considered because noise from first stage will not be noise-shaped. Four-input comparator is adopted to construct Flash multi-bit quantization to reduce power dissipation. Finite switch-on resistance and switch non-linearity are also the key of design, thus switch needs careful design to avoid system harmonic distortion result from switch non-linearity. The modulator is designed under CMOS 0.5um process. The system which used DWA and IDWA were simulated in Cadence respectively. Results shows that noise floor of system which used IDWA is under-120 d B and ENOB is 16 bits. The total harmonic distortion is smaller than-100 d B.Finally the thesis also presented the design of digital decimator. its passband ripple is smaller than 0.01 d B and stopband attenuation is smaller than-70 d B.