Design Of Digital Gyroscope Sigma-Delta Modulator

With the rapid development of integrating technology, the function of digital integrated circuit applied in signal processing system for signal storage and computing is becoming more and more powerful. However, the sensor and interface circuit of sensor which are used to sample analog signals in nature constrain the performance of the whole system. Digitalized gyroscope sensor as an important part of MEMS sensor is widely implemented in military and commercial electronic products. In order to digitalize the gyroscope sensor, a high resolution ADC is necessary. The Sigma-Delta modulator is a crucial element in Sigma-Delta ADC since it decides the converting resolution or even the precision of the whole digitalized gyroscope sensor. So it is of great importance to design a high resolution and low distortion Sigma-Delta modulator for ADC.Recently the research about the noise and harmonic distortion of Sigma-Delta modulator is not perfect and there is much work to be done. This dissertation mainly focuses on the analysis about noise and harmonic distortion. Then a high resolution and low distortion Sigma-Delta modulator is designed. This dissertation introduces the working principle of Sigma-Delta modulator and then the system level design of fourth order full feed-forward modulator is finished by Matlab. While analyzing noise in the modulator, all the noise sources are equaled to the input or output of each integrator. The main noise sources are the noise of operational amplifier of the first integrator,white noise of on-resistance of the first integrator and the second integrator and the aliased noise in switched capacitor circuit. After analyzing harmonic distortion sources, non-ideal models in Simulink were built and some circuit simulations were done to verify the effectiveness of analysis. The main harmonic distortion sources were nonlinear setting error of integrators, nonlinear on-resistance of switch and nonlinear capacitors.The full differential switched capacitor Sigma-Delta modulator is designed in standard 0.35 um CMOS process. Double sampling and chopping techniques are used to double signal bandwidth and eliminate 1/f noise. After designing low distortion gain boost one stage folded cascade operational amplifier, CMOS switch, comparator, full feed-forward adder and other circuit elements, the layout is drawn. Then the test system is designed. While testing the chip, the modulator is powered by 5V supply voltage. For the sampling frequency of 2.5MHz, its power consumption is 9m W and the maximum input amplitude is-3d BFs. The 1Hz dynamic range is about 132 d B. The maximum signal to noise ratio is 89 d B and the dynamic range is 92 d B for the signal bandwidth of 10 k Hz.