Research And Implementation Of Digital Module For High-precision Audio Σ-ΔADC

Σ-ΔADC is widely used in high-end digital audio systems for its high pricison,good linearity and low requirement for anolog circuit. The mojor technology used inΣ-ΔADC is oversampling, noise-shaping and digital decimation filter. Digital decimationfilter is critical for the design of Σ-ΔADC with high performance. Compatibility ofmultiple digital audio formats is necessary for Σ-ΔADC used in high-end audiosystems. This thesis has two objects, one is to design a digtal decimation filter that hashigh precision and multiple decimation rate, the other is to design a audio interfacecircuit that is compatible of multiple digital audio formats.This thesis firstly studies the operating principle of Σ-ΔADC and the designmethod of digital decimation filter, designs a multi-stage decimation filter structure thatcan implement128/64rate decimation. This structure is composed ofcascaded-integrator-comb filter, compensation filter and halfband filter. Matlab is usedto design each stage of filter that can satisfy design specification and Simulink is uesd todo behavior-levle simulation to verify the function and performance of the designedstructure. Secondly, the principle of double-channel audio interface is studied and anaudio interface circuit structure compatible of I2S format, left justified format and rightjustified format is designed.This thesis also studies the time division multiplex technology for multiplier,which can effectively reduce the circuit area. Verilog HDL is used to write effectiveSynthesizable code for digital filter and digital audio interface. ModelSim, QuartusIIand FPGA board used to verify the function and performance. Finally, synthesis tooland other back-end tools are used for synthesis, place&route, formal verification, statictiming analysis, DRC, LVS and post-layout simulation before GDSII layout file issubmitted.The designed filter can implement128/64rate decimation, has20kHz bandwidth,pass-band ripple smaller than0.01dB, stop-band attenuation larger than70dB, SNRlarger than104dB, ENOB about17bits. The audio interface can support I2S, leftjustified and right justified format. The design is implemented with65nm technology, and the total area of digtal circuit is440×440μm2. The layout of digital circuit haspassed the post-layout simulation and physical verification. Both the function andperformance come up to the expected requirements.