A Block-Level Verification On Audio Module Of STB Based On UVM

With the development of digital media technology,the mutual adaptation of audio content and listening scene,the development of voice interaction and audio playback technology,all of which enable audio intelligent hardware to realize the touch of users and audio content in each scene.The emergence and practice of concepts such as internet of vehicles and smart home have promoted the development of on-board audio,intelligent audio and other hardware.It can be said that the development of mobile audio is abundant,and the types of accepted devices are gradually increasing: smart phones,internet of vehicles,set-top boxes,wearable devices,smart home etc,and people are increasingly pursuing highquality audio experience.Audio technology is not only a hot project today,but also the key competition target of many companies in the future.In general,people's requirements for audio are getting higher and higher,and the application scenarios of audio are becoming more and more intelligent,the development of audio will be endless.For new and increasingly complex applications such as audio,verification is essential which in order for the chip to be able to tape-out smoothly and take advantage of the market.The design verified in this thesis is the AUDIO?TOP which is a subsystem module of XXXX,a high-performance STB(Set Top Box)intelligent chip which i participated in during the internship.How to build a highly reusable module-level verification environment of AUDIO?TOP module based on the idea of UVM verification methodology and using System Verilog verification language,and to complete the verification of AUDIO?TOP module efficiently and completely are the core work of this thesis.This thesis first makes a detailed study of UVM universal verification methodology,including the analysis of its classical architecture composition and the functions of its main universal verification components.Furthermore,the connection between these common verification components and the operation mechanism of the whole validation environment are studied and analyzed in detail.At the same time,it analyzes the excellent operation mechanism of UVM and the convenience brought by these operation mechanism to the verifier.Then this thesis analysis the functional architecture of the audio module and analysis the audio specification which used in audio module,such as I2S?SPDIF?PCM and the processing of the corresponding modules of these module specification,then the functional test points were extracted,and the verification plan was proposed considering the reusability and readability of the verification platform.All these provide a theoretical basis for building a verification platform.Based on the central idea of UVM verification methodology,the system verilog language is used to implement each component of AUDIO?TOP verification platform,and the verification environment of AUDIO?TOP module is built according to the verification scheme proposed in the early stage.In the realization process of the verification environment,considering the reusability and readability of the verification platform,the corresponding optimization and improvement of the platform structure are carried out,and finally a complete and highly reusable AUDIO?TOP verification environment is obtained.At the same time,the subsequent verification of AUDIO?TOP module is completed on the basis of this verification environment.According to the function points extracted from the verification scheme,to build the test cases and sequence library.Finally run all test cases and keep running regression to generate the coverage report.The code coverage is 98.86% and specify code that is not covered.The function coverage is 100% which indicates that all function points have been verified successfully.This verification platform can be reused to the system-level verification platform,and both the module level and system-level verification can meet the project requirements.