Research And Imjplementation Of High Precision DAC Testing Method Based On FPGA

The test is the extremely important segment in the chip research and design. Itcosts a lot to verify chips’ functionality and test chips’ defect, furthemore the cost ofmixed analog-digital circuit test chip R&D accounts for most of it. In addition to theimprovement of the cost is exacerbated by the expensive test equipment, it has to facethe challenges of testing accuracy and efficiency while testing a high-precision DAC.But for general chip designers, the more realistic significance is to verify theperformance of the chip within the limited resources and time, so there should be alow-cost, high-efficiency, convenient and flexible testing scheme when testing highprecision DACs.The paper designs a high-precision DAC test platform based on the FPGA,including the FPGA implementation of digital signal generator, test board equippedwith the chip under test and test analytical instruments. First, the paper analyzes thebasic test method of the DAC parameters and the input signal, as well as the resultsobtained from the measurement of the parameters required, to determine the staticparameter measuring method based on the key points and the dynamic parametermeasuring method which takes DDS as the core. And it also analyzes the problems thatmay occur during the test. Second, the paper analyzes the advantage of the FPGA inchip testing, as well as working principle of the DDS in detail, and designs a digitalsignal generator based on the FPGA. The experimental results show that the signalgenerator can provide test vectors for high-precision DAC test. Third, the testingplatform has been built; including the detailed design of the test circuit and PCB testboard design, as well as the test platform debugging. Finally, the author uses the testplatform to complete the12-bit segmented current-steering DAC testing.Test results show that the test platform designed in this paper does work at bothstatic parameter test and dynamic parameter test, and it is a kind of agile, rapid andlow-cost test scheme for the other chip designers to use.