The Research On Test Data Processing Technology For Concurrent Core Test Reusing NoC

With the development of SoC architecture from bus to NoC, More and more IPcores are integrated on single chip, it makes test access become difficult, the test timeand test data volume also increases, and it requires multiple ATE channel supportconcurrent testing in traditional test. Therefore, this dissertation expanded the studieson test data processing technology for concurrent core test reusing NoC, the maintasks are as follows:(1) Investigated present research situation of test data compression and test,explained the test necessity and process of test, and gived some introductions on testbasic knowledge related to the dissertation.(2) This dissertation proposed a new method for merging test sets based onmultiple scan chains, the test set whose test vector is long is selected as targeted testset, to merge the other one in the form of scan slices. The algorithm can compressestest data reaching42.8%which is higher than Similar scheme，reduces the powerconsumption of shift test bits, reduces test time, reduced number of demanded ATEchannel，simplifies the design separation architecture hardware. More importantly,improves the capability of test access by reusing NoC architecture.(3) Shared test set mentioned above bringed severe challenges in ATE operatingfrequency and channel bandwidth due to distribution of care bits. So a new methodof test data compression/decompression is proposed based on few same or differentbits between different blocks. The low frequency data blocks associated with thehigh frequency data blocks which participated in the huffman encoding by few sameor different bits, and shared shorter huffman codeword with them in a certain way,which can simplify the state table of huffman coding and achieve the purpose of testdata compression. According to experimental results, compression ratio increases by6.11%to22.89%compared with the other schemes, and the proposed method issimple.This dissertation has an important role and significance for the realization ofconcurrent test based on network-on-chip architecture.