Architecture Design And System Modeling For16-bit Pipelined ADC

Analog to digital converter (ADC) is the core device which combines the digitalworld and the analog world in the modern electronic system together. Pipelined ADCis a main structure of ADC with high performance, due to its accuracy and speed.With the development of the pipelined ADC with high performance and thecontinuous rising of the complexity of circuits, the system level design becomes anindispensable key link before the circuit design. How to optimize power consumptionand noise in system level and determine the optimized system architecture and how tobuild pipelined ADC and non-ideal models, which can provide theoretical guidancefor the following circuit designs, are the keys of system level design of pipelined ADCwith high performance.This thesis first introduces the entire system of the pipelined ADC and thestructure type of its key modules (such as SHA, sub-ADC circuit, MDAC circuit anddigital delay correction circuit, etc.) and determines the architecture design and circuitstructure followed by the system modeling in the thesis. Secondly, according to thelimitation of the non-ideal factor to the first stage, the reasonable3.5-bit stage-resolutions can be compromised; with the important parameters of the powerconsumption, noise tolerance and system sampling capacitance value, according to themethods of minimum comparator number algorithm, the sampling capacitor scalingtechnique and different accuracy comparison methods, the thesis optimizes the systemperformance and selects two relatively reasonable architectures (3.5+2.5×5+3) and(3.5×2+1.5×6+3); and at the system level, the thesis determines the key parametersof each pipelined stage, such as the open-loop gain, the sampling capacitor, unity gainbandwidth and so on. Lastly, the thesis designs the system model and simulates thenon-ideal effect such as the ideal16-bit pipelined ADC and noise, clock jitter,capacitor mismatch, not fully established signal, limited open loop gain, etc.,compares the performance of the two different architectures and determines theoptimum system architecture; According to the design parameters determined bysystem level, the thesis designs and simulates16-bit pipelined ADC circuit.The thesis employs the Simulink software to design the system level model of the optimized16-bit pipelined ADC. With the condition of the temperature398k, the100MHz sampling frequency, the9.998MHz sine wave signal, the thesis simulates themodel, and tests the result by FFT. The simulation results show that the architecture(3.5×2+1.5×6+3) has superior performance, of which the SNR, SFDR and ENOB canachieve90.33dB,113.19dB, and14.71bit.