The Design Of High Speed CDR Circuit For10G-EPON

As the increasing demand for low cost, high capacity and high quality services, theaccess network technologies have been evolving from copper-based digital subscriberlines (DSLs) to fiber-to-the-home (FTTH) based on optical fibers. Among these FTTHs,since10Gbit/s Ethernet PON (10G-EPON) is completely compatible with the current1G-EPON system and benefits from both10G-Ethernet and passive optical network, itbecomes the most promising one. It has been known that clock and data recovery circuitis the most critical component in the physical layer of10G-EPON and is also thebottleneck for improving interfaces’ speed.Presently most of the high speed CDR circuits based on CMOS technology havebeen employed in10Gbit/s (or above) optical communications. So the research focus ofthis paper is chiefly on the design of a10Gbit/s CDR circuit based on SMIC0.13μmMS/RF1P8M CMOS technology, which is completely compliant with10G-EPONstandard. The main contributions from this paper are listed as below.(1) Based on R. C. Walker model, novel equations are developed to evalutate jittertolerance in terms of random jitter and to derive the minimum value of stabilityfactor (also the minimum value of loop capacitor), wich improve the integrationof CDR circuits.(2) Based on the above models, a novel design flow is proposed to map the paramtersfrom10G-EPON systems to CDR circuits, which provides a good example for theinitial design of high speed CDR circuits.(3) The author chooses the half-rate nonlinear CDR topology, which mainly consists ofmodified half-rate Alexander PD, high speed charge pump, loop filters and QVCObased on cross-coupled LC oscillators. And the modified half-rate Alexander PDhas been accepted as a patent.Simulation results of the CDR circuit show that the jitter tolerance is larger than0.28UI@4MHz, the jitter generation is less than0.094UI, the clock offset is less than0.254UI and the jitter transfer curve is always below the required curve from10G-EPON standard. Measurement results of the QVCO show that the it can achive a tuning range of15.1%from4.71GHz to5.48GHz, the gain of this QVCO is about1.1GHz/V and the phase noise at1MHz offset is about-107.1dBc/Hz. In conclusion,the CDR circuit is completely compliant with10G-EPON standard.