Study Of Switching Loss Model And New Structure Of SiC MOSFET

Silicon carbide?SiC?becomes a competitive candidate to fabrication of core power device in power electronics due to its superior properties involving wide band gap three times wider than silicon,high critical breakdown electric field,competitive thermal conductivity,and fast carrier saturation drift velocity.For another thing,the metal-oxide-semiconductor field-effect transistor?MOSFET?as a full-controlled power switch,features fast switching,high input impedance,and relative easiness to drive.Therefore,the SiC MOSFET takes full use of the talent intrinsic properties of SiC material,as well as unipolar transportation mechanism.SiC MOSFET characterizes not only high blocking capability,but also excellent conduction capability,similar like silicon insulated gate bipolar transistor?Si IGBT?.Furthermore,the significant reduction of parasitic capacitances and less minority carrier storage phenomena for SiC MOSFET enable faster switching speed and lower switching loss,as a requirement for increasing power device operation frequency.The benefit of high frequency application could translate into significant enhancement in efficiency,volume,mass,and comprehensive cost of power electronics.However,the dynamic performance of SiC MOSFET still does not reach its entitlement and the switching loss of SiC MOSFET thermally limits the upper limit of the switching frequency of power electronic application.Therefore,it is of necessity to establish related theory to inestigate the nature of switching,and propose feasible schemes to reduce switching loss of SiC MOSFET,enhancing power electronic applications further.In order to maximize the practical value of SiC MOSFETs in power electronics applications,this dissertation focuses on the key challenge technique with the ultra-fast switching speed and ultra-low switching loss of SiC MOSFETs,and conducts studies of building theoretical models and proposing new structure device.Conclusively,the innovation of the dissertation includes establishment of multi-level switching loss models,the development of two new trench MOSFET and high-frequency low-loss integrated power module under the guidance of the models.1,SiC MOSFET device and circuit level switching loss modelsBased on the physical mechanism of charging and discharging of parasitic capacitances of SiC MOSFET,the switching loss model is established,which can reveal the nature of swithing and explain the reasons why the deviation exists between the proposed loss measurement method and the commonly accepted dynamic loss method.Although the proposed total switching loss model is consistent with the conventional one,the conventional loss model is underestimated the energy stored in the output capacitance of the SiC MOSFET C_oss,i.e.,E_oss,during turn-on process;and the conventional loss is overestimated E_oss during turn-off process.For the case of the device in the soft-switching mode,the conventional loss calculation method is incorrect.The model clarifies the factors that control the dynamic characteristics of SiC MOSFETs at the device structure level.For turn-on process,Miller capacitance C_gd and C_oss are the main factors that restrict the loss,and the driving ability and C_gd are the main factors that determine the speed.While the load current is the predominant factor to turn-off loss,moreover,the load current and C_oss play significant role to control the turn-off speed.The model theoretically proves that the minimum turn-on loss is close to E_oss,and quasi-zero turn-off loss could happen under certain conditions.Based on the proposed device-level switching loss model and a variety of theoretical backgrounds?structure and mechanism of semiconductor power device,power electronics applications,signal and system,and analog integrated circuit?,the second-order circuit switching loss model for SiC MOSFET is established also.The model reveals the effect of parasitic inductances at different positions of the MOSFET on the dynamic loss.During modeling process,it is analyzed that the influence of the common source parasitic inductance L_s and the gate loop parasitic inductance L_g on the dynamic loss in different switching intervals.In detail,the analytical expressions of t_ronon and t_gdon are achieved in the process of modeling.In the t_ron interval,the time constant is g_fsL_s+R_gC_gs.In the t_gdon interval,the duration of this interval depends on the number of charges on the C_gd and the discharge capacity of the gate loop.The L_s and L_g on the source and gate terminals have little effect on the discharge process of C_gd.2,SiC MOSFET and gate driver co-package moduleBased on the theoretical guidance of the device-and circuit-level models,a SiC MOSFET die and gate driver chip co-package integrated module for high frequency applications is developed.The integrated module utilizes the Kelvin connection to remove the L_s and significantly reduces the L_g and the power loop parasitic inductance L_d.There are clean dynamic waveforms without adding any external gate loop resistance,which achieved a desirable tradeoff between switching loss and electromagnetic interface.Through the utilization of zero-voltage switching mode can remove the inherent loss E_oss and make full use of quasi-zero turn-off loss theory,1.5MHz synchronous boost converter is demonstrated based on the integrated modules,in which a SiC MOSFET loss is just 10W.Moreover,the input voltage of 700V,3.38MHz half-bridge inverter is also demonstrated,in which a SiC MOSFET loss is just6W.3,low loss trench MOSFET:ITS-TMOS and SG-TMOSA SiC trench MOSFET?TMOS?with integrated self-assemble three-level protection?TLP?Schottky barrier diode?SBD?,named ITS-TMOS,is proposed.The device features the integrated TLP-SBD that remarkably low V_on and low leakage current due to the three-level protection from TMOS iteself,avoiding bipolar degradation issue and enhancing the robustness of power module.The optimized ITS-TMOS and the conventional TMOS are taken as an example.The ITS-TMOS exhibits smaller reverse conduction voltage(V_on=1 V)and its total gate charge Q_g?971nC/cm²?is 18%smaller than Q_g?1177 nC/cm²?of the conventional structure.The shielded gate SiC trench MOSFET?SG-TMOS?is proposed also.The influence of the shield gate on the conduction loss and dynamic loss is comprehensively anlyzed from the physical mechanism point of view.Due to relative large depletion aroused by the P+shield region under the bottom of the trench,the shield gate in the trench gate,and the Pbase region,an anti-excessive depletion?AOD?layer is introduced to guarantee decent conduction capacity.The 900V SG-TMOS exhibits R_on of less than10 m?·cm² and Q_gd of less than 24 nC/cm².4,fabrication and characterization of SiC MOSFETBased on the domestic fabrication platform,a 1200 V/5 A SiC MOSFET is successfully designed and fabricated.Moreover,the three-section adjusted field limited rings structure is proposed and fabricated.Furthermore,the devices are subjected to high temperature reverse bias?HTRB?test(175 ^oC,V_ds=1360 V,168 hours).The results show that the leakage current is less than 0.1 mA/cm²,and the variations of blocking voltage,threshold voltage,and on-resistance of the devices are less than 10%,which verifies the high robustness of the devices.In brief,based on the SiC MOSFET device itself and the oriented actual power electronics high-frequency application,the desseration proposes theoretical switching loss model and takes attempt to reduce SiC MOSFET dynamic loss from the device structure,process,and power module optimization,promoting the application of power electronics field development.The study exhibits certain reference values.