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The Study And Design Of 250V Radiation Hardened VDMOS

Posted on:2016-05-15Degree:MasterType:Thesis
Country:ChinaCandidate:W DuFull Text:PDF
GTID:2308330503977120Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
VDMOS is widely applied in the field of spacecraft. When irradiated, the parameters of VDMOS may be affected by the TID, such as the drop of breakdown voltage, the drift of threshold voltage or the change of on state resistance, and so on. These phenomena make the spacecraft performance decline. Besides, the radiation may result in SEGR or SEB, which are unrecoverable damage on VDMOS. Therefore, the study on radiation reinforcement method for VDMOS is of great significance.Based on the basic structure and main parameters of VDMOS, three effects(SEB、SEGR and TID) generated by radiation have been studied in detail. With the TSUPREM4 and MEDICI, the processes of SEB and SEGR are analyzed, and a better explanation for the physical mechanisms about them has been gotten. Analyzing the drain source breakdown characteristic curve, the relationship between the second breakdown voltage on VDMOS and the SEB safe work area is confirmed. In order to illustrate the longitudinal electric field distribution during the damage process of SEB, the method of integrating longitudinal charge curve is proposed. By the semi empirical formula of SEGR, the theoretical model for analyzing SEGR is established. According to the model, the effects of ion species、incident position and width of JFET on the SEGR critical conditions have been researched. Three conclusions show that the bigger ion atomic number, the incident position closer to the middle of JFET region and the wider JFET region are worse for restraining SEGR. Then, the radiation hardened methods for SEB and SEGR are studied. Both the parameters of P+/N+ process and buffer layer can affect the safe voltage for SEB. After a detailed analysis, the conclusions indicate that the larger concentration difference between P+ and N+ more likely triggers SEB. In addition, VDMOS with buffer layer has better ability to resist SEB and the optimum parameters of buffer layer can be found by MEDICI. Lastly, a new anti SEGR VDMOS device structure is proposed in the paper. The comparison of SEGR critical conditions between the new structure and the traditional structure proves that the new one is more conducive to the suppression of SEGR.An anti-radiation VDMOS device with 250V of breakdown voltage, 12A of current,0.22Ω of on resistance and 2-4 V of threshold voltage has been devised. By the TSUPREM4 and MEDICI, the electrical parameters and technological process are designed. The layouts are drawn by Cadence. The simulation results show that the designed VDMOS meets with the requirements.
Keywords/Search Tags:radiation harden, VDMOS, simulation, SEB, SEGR, TID
PDF Full Text Request
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