Reversible Logic Design And Application For Delay In Circuit

Reversible logic design is an essential part of reversible logic research. And it plays an important role in the field of low-power circuit design, quantum circuit design and so on. Since the reversible logic circuits are information loss-less, it has the low-power feature. Reversible logic design is an important part of the implementation and optimization of the reversible logic circuits. In recent years, reversible logic design becomes a hot research topic, which with the reversible logic depth research.The optimization goal of these existing methods of synthesis is to reduce cost of merit. Such as, the number of logic gates, quantum cost, the number of lines, as well as the running time consumed by synthesis methods. Delay is an important factor in evaluation of reversible logic circuit design, but rarely been considered. In the actual circuit, the glitch produced by different transmission delay of circuit is likely to increase the power consumption of the circuit. Reducing delay of circuit will not only promote to improve performance of the circuit and reduce the power consumption of it, but also find a new way for the reversible network synthesis. But for special constraints of reversible logic design and unique technical requirements and limitation in reversible circuit treatment, some challenges will be taken during the study of the problems. In this paper, we develop the research on problems of delay in reversible circuit. Some issues are discussed in the following aspects.1) We build delay model of reversible network. And then present an algorithm to calculate the delay of reversible logic circuit. The algorithm can be used to calculate the delay of the reversible logic circuits synthesized and optimized by several different reversible logic synthesis methods.Through the Benchmark we analyze the performance of these types of reversible logic synthesis method in the level of delay. We get the conclusion that there is no direct relationship between of the quantum cost and delay.2) To reduce the delay of reversible network, this paper proposed optimization algorithm was based on moving and simplification rules of sub-sequence of reversible network. The algorithm scanned reversible network from left to right and right to left, respectively. If there was the case that satisfy the delay optimization rules, then optimized. By contrasting the both delay result from the algorithm, we can get the network with less delay. By using the whole internationally recognized3-varibles functions and some representative part of examples in the Benchmark to validate it, the results show that the delay in reversible network can be reduced effectively and the cost of reversible network is decreased.3) In order to better analyze the impact of delay in practical application of reversible logic design, a design of BCD code synchronous/asynchronous decade counter based on reversible logic gate is put forward. For the purpose of reducing delay, we choose to use the module with relatively small delay and quantum cost, and do a comparative analysis of performance on this design at the level of delay, quantum cost and reversible gate count.