The Application Of HDLC Frame Transceiver In TDM/Ethernet Interface Circuit

The HDLC is a bit-oriented link control procedure which is worked on data-link layer. It is widely used in kinds of industrial control applications. In this paper, based on the background of TDM/Ethernet interface circuit and researching of HDLC standards and contents, a kind of HDLC frames transceiver based on FPGA is designed and used in the TDM/Ethernet interface circuit.Firstly, on the basis of a detailed analysis of HDLC frame format, the feasibility of implementation of HDLC protocol is discussed. Compared with several commonly used implementation methods and summarize their respective features in order to explain the advantages of FPGA method. With the top-down design idea, the system is divided into several big modules and the big modules are further divided into single function parts to reduce system complexity.It is also beneficial to modify and integrate the system.Secondly, based on the software Quartus II of company Altera and hardware description language, implementation process of each module is introduced in detail and the flow chart of main modules are given. In the design and implementation of the transmitter, zero-insert module and crc-check module,send-cash module are mainly introduced, what’s more, the design of transmitter state machine is also Described and the detail state transition diagram is given. In the design and implementation of the receiver, zero-remove module and flag-processing module are mainly introduced. Moreover, the logic circuit diagram and timing simulation results of the system is illustrated and analysed to prove the correctness of the design.Thirdly, the HDLC frames transceiver is used in the TDM/Ethernet interface circuit after simplifying and modifying. On the basis of searching material and analyzing requirement, a method of TDM/Ethernet interface circuit based on FPGA is designed. The core of the design is the speed conversion from Ethernet frame data to one channel E1.In the sending process, the Ethernet frame data should be captured by the MⅡ interface of the PHY chip and cashed in a FIFO after a change of4/8.Then frame the data by HDLC protocol and saved them in the external SRAM, at last the data should be sent serially and a pause frame should be sent to the sending end in order to control the speed when the number of HDLC frame is equal to certain amount. The receiving of data is a reverse process of sending process. In the receiving direction, data speed changes from low to high so that the data-cash problem dose not exist.The timing control is the only thing which is needed to pay attention to in order to meet the demand of PHY chip. Finally, download the entire design to the circuit and test the function of it. The test result is illustrated and the working of the circuit is proved normal.