Design And Validation Of HDLC Channel Aggregator

Based on analyzing webmaster converging of the Access Network, the aggregator is studied by using top-down design flow of digital integrated circuit. It divides the aggregator into functional modules by analyzing HDLC protocol and SDRAM cache regulation. Each module was designed at the behavior level using VHDL (VHSIC hardware description language), compiled and simulated by ModelSim SE 6.3. The synthesizing and test of the aggregator was completed under ISE EDA synthesizing condition. The netlist was implemented based on the Fujitsu cs86 standard unit library.In this design multi-channel HDLC framer and deframer is achieved. The SDRAM was used as caching space for HDLC data. Using Active Queue Management, we controlled the multi-channel datas and changed 63 channels into 1 channel. Using time-sharing management, the processing speed of datas is increased, and the resource is saved. The netlist is available for the following IC physical design after static time analyse.