Research And Implementation Of Convolutional Coding And Viterbi Decoding Based On FPGA

In the digital communication, Error control coding (Error correcting coding) is an effective method to improve reliability of signal transmitting, and its action is more and more important. Error correcting code mainly includes block code and convolutional code. The performance of convolutional code is superior to block code if their corresponding encoders are the same complicated degree.Algebraic decoding and probabilistic decoding are chiefly method for convolutional decoding, Algebraic decoding is based on the algebraic structure of convolutional code, but probabilistic decoding is based on not only the algebraic structure of convolutional code, but also the statistics characteristics of signal channel, its specially characterist is drawn out, so error probability for decoding is very low.The design of convolutional code decoder began from high performance and complicated decoder, for the first sequence decoding, its error probability for decoding would be very low when constraint length is increased. Later, the decode developed slowly towards to low performance and simple decoder, Viterbi algorithm is very utility for short constraint length. Viterbi algorithm is a maximun-likehood decoding method. When constraint length is not long(≤10) or requirement for bit error rate is not high(about 10-5), algorithm for Viterbi decoding is high efficiency and fast speed, and the decoder is also simple.Design for encoder and decoder of convolutional codes is introduced in this paper. At the same time, realizable scheme with FPGA is researched. Technology of interleave and deinterleave is applied in the procedure of coding and decoding.In the fist place, the ABC of convolutional codes and the basic principium of algorithm for Viterbi decoding is briefly introduced, and the difference between hard-decision and soft-decision is analyzed . the next in order, Technology of interleave and deinterleave, Including its application in Error Control Coding. the 3th, application FPGA, the hardware resource, and Quartus II, the soft of development environment are introduced, Including the designing method and the designing rule of digital system. the 4th , encoder and each module of Viterbi decoder is designed and corresponding decoding algorithm is applied, the algorithm is realized with FPGA . At last, encoder, hard-decision decoding and soft-decision decoding ,the usage of interleave and deinterleave are simulated in Quartus II , then the function of Viterbi encoder is analyzed according to the result of simulation.The result of analysis denominate that bit error rate of system has achieve the requirement of design, and the implementation of design for decoder is verified, parallel Viterbi decoder designed with FPGA is fitted for high speed data transmission.