As the scale of integrated circuits reaches the nanometer level, the interconnectdelay which is one of the most challenging problem in IC design, has significantlyaffected the performance of IC. This paper mainly focuses on the analytical modelingof nanometer scale interconnect delay. In the paper, the traditional method whichdescribed interconnect by non-coupled lump circuits has been improved, and a moreaccurate delay result has been obtained. The paper first obtains the results of R, L, Cparameters of top level interconnect of nanometer IC, and then an analytical delaymodel considering couple effect is proposed using decouple calculation method andtelegraph equation. It shows that the interconnect delay result is very accuratecompared with SPICE. Meanwhile, the simulation time has been greatly shorted whichproves the high efficiency of the model. The interconnect delay model proposed in thispaper has unique advantages and potential applications in VLSI timing analysis andoptimization. |