Research On AES Encryption Algorithm And Implementation Of Its IP Core

Since the20th century, The rapid development of information technology brings usinto a new era of information technology, meanwhile, the problem of informationsecurity is more and more outstanding. In2001, National Institute of Standards andTechnology (NIST) issued the Advanced Encryption Standards(AES). AS the nextgeneration symmetric-key algorithm which is to replace DES, its safety performance isbeyond argument.The work of this thesis originates from: horizontal subjects “the development ofsecurity chip in smart grid”. It needs to design an IP core of encryption chip whichcould effectively preserve personal privacy information and important data for smartgrid security requirements. After the in-depth research and analysis of AES, this thesisproposes an AES IP which could support AES-128mode, be compatible with Wishbonebus.This thesis firstly introduces and analysis mathematical basic knowledge andrinciple of AES algorithm and makes appropriate changes on round functions on thisbasis, then proposes an equivalent encryption structure which could integrate theencyrption and decryption part in one hardware.In addition, this thesis also researches and analysis the combinational logic methodto implement S-box reducing the complexity of finding inverse from composite fieldsGF(2~8)to GF((2~4)~2), and integrates the two S-box in encyrption and decryption inone merged optimized S-box; on the basis of the advantages and disadvantages of twomethods implemention on InvMixcolumn, one degisn that two methods aresimultaneously used in the datapath and resource sharing is proposed and improved.One encyrption and decryption resource sharing key schedule unit which could besynchronized with the computation of round function and expand in an on-the-fly waywithout any memory is proposed, on the basis of all above work, proposes an AES IPwhich could be compatible with Wishbone bus.Finally, joins the IP with the encryption SOC system by Wishbone bus, theOR1200CPU executes assembler language instructions to control the IP core to work,and given a FPGA verification on the FPGA development board based on XilinxVirtex-2XC2VP30, Results prove that this desgin is fully comply with the standardAES.Our design of AES IP core’s working mode is feedback, it can reach datathroughput of1.333Gbits/sec at the operating frequency of14.565MHZ, Theperformance is significant improved compared to the other literature in key schedule,the degisn of S-box and architecture of hardware.