The FPGA Design And Implementation Of Time Triggered Ethernet Node Card

Nowadays,with the enlargement of the distributed network application,new requirements of certaincy,real-time and fault-tolerant have been put forward on traditional distributed network.In order to achieve these requirements,early researchers proposed the concept of time triggered networks which turns event-triggered network affairs into time-triggered network affairs to improve the network performance.Firstly,this thesis makes a comparison about TTCAN,FlexRay,TTP and TTE.Secondly,the thesis analyzes their advantages and disadvantages.Finally,according to the development trend of the current network,the thesis decides to adopt TTE network as the research direction.TTE introduces the concept of time synchronization in the Ethernet.Time synchronization can compensate the local clock jitter of each node in the network and make the network node using the scheduled table to complete the sending and receiving of time-triggered affairs.This concept makes sure that there is no conflict when the timetriggered affairs transfer over the network.The current mainstream methods of time synchronization are IEEE 1588 and SAE AS6802.Through the analysis and comparison of the two methods,this thesis concludes that SAE AS6802 is superior to IEEE 1588 in terms of the flexibility of network topology and synchronization reliability.Therefore,SAE AS6802 is used as the standard of time synchronization in this thesis.In this thesis,the processing of ET frame and the timestamp position are improved in the whole design process.The ET frame cutting and recombination are proposed to improve the bandwidth utilization of ET frames.The timestamp position is moved to the hardware interface to improve the timestamp accuracy.Real-time monitoring of the physical link is proposed to improve equipment reliability.The design also allows the upper layer application to make dynamic configuration in the node card,which improves network configurability.The overall design is divided into three parts.The first part is the Ethernet data link function.The second part is the time synchronization of the TTE network and the TT frame triggered process.The third part is the DMA function.This function mainly achieves the data interaction between the node card and the upper application.The realization of the overall design depends on FPGA,because the FPGA performance is reliable and the design cycle is short.After the completion of the overall design,the design is tested through the Mentor Canpany's ModelSim.The simulation method uses white-box verification which makes sure the code coverage.The board-level test adopts a software and hardware combination method,using the TTE application software and the scheduled table software to complete the TTE network function test.