Cost-Efficient SHA256 Digital Encrypt System Based On FPGA

Currently, efficient hash algorithm is a hot research field of the security. In this paper, Based on the research of SHA256 (Secure Hash Algorithm) in the FIPS180-2(Federal Information Processing Standards) Standard, and combined with the unique features of the hardware programming, then implement the SHA256 algorithm and WISHBONE bus on the FPGA (Field Programmable Gate Array).Traditional software implementation of SHA256 algorithm, during the encryption, it will take a lot of CPU times, and it also contains the risk of force brute and other security issues. This encrypt system is using the PCIe4BASE FPGA card of CESYS company. And implements the encrypt system on the Xilinx Virtex4 XC4VLX25 FPGA chip by using VHDL program language. To improve the system operating frequency on the target board, the data pipeline and parallel processing technology is using in the SHA256 algorithm implementation. To utilization of the programmable resources, another resource BRAM (Block RAM) in the FPGA is used as intermediate data storage media to reducing the use of FPGA programmable resources Slices. Ultimately, after the Place&Route. The max operating frequency is 125.187 MHz, and the data throughput is 942 Mbps. The SHA256 core will take 68 clock cycles to finish processing on 512bits data block. At last, after compare then software and hardware encrypt system of the SHA256 core, the hardware encryption system contains more advantage and full of logging.