The Implementation Of DFT For A High-performance Processor

With the development of DSM (Deep Sub-Micron) manufacture technology and the reuse of IP (Intellectual Property) cores, the SoC (System-on-Chip) design method becomes more and more popular. DFT(Design For Testability) has played an important role in the high performance processor design process, which is a challenging work.The main topic is the DFT of a high-performance processor, the chip design use45nm process, and the frequency is1.2GHz. The chip’s logic module structure is complex and the use of DDR3, PCIE, SATA, USB high-speed IP core. which brings a greater challenge to the processor design for testability. In order to achieve the chip test goals and improve the chip testability, we mainly adopt following DFT method:scan design, memory built-in self test, boundary scan, which provides a convenience and reliablity for chip.After briefly discussing basic DFT theory, methods, and the structure of the chip, this article focuses on the implementation of the processor’s DFT, and the chapter analyses the difficult part in details. Through the DFT of entire chip, the main research of this paper can be summarized as following:1、By using at-speed method, we have solved the complex problems such as clock domains, clock gating and compression logic,and so on. In result, the chip meets the desired test requirements with transition fault coverage reaching about90%, stuck-at fault coverage96.31%.2、By "low power fill" technology, the efficient low power test vector of scan design has been generated, the specific method is that each attention bit value of test vector is copied into the scan chain’s follow-up bit, until the next one is opposite to the former one and low power test vector is generated. By this method, a single module scanning power can be reduced22.46%than normal conditions in average.3、Due to the number of memory in the chip is very large, if using the general design method, the test power of MBIST will be very high. This paper has reduced MBIST’s power by such a method that according to the clock domains and memory’s size, memories can be divided into different groups, and between groups are serially tested, internal groups are parallelled tested. Compared with the traditional test power consumption, test power is reduced by14.36%by this method finally.At present, the DFT of the chip has been completed, and the chip is in the tapeout stage, the entire chip’s DFT structures have all been through the carefully simulation and verification, which shows that the design meets the test demands.