| Serial data communication has gained wide application in network transmission,backplanetransceiver and I/O interface. With the development and growing of interconnection technology,RapidIO has become a mainstream technology in high-speed serial data communication.RapidIO is the system-level and chip interconnection technology, which is mainly applied inhigh-performance digital signal processor systems, embedded systems and the communicationof chip interconnection. Because some non-ideal factors such as crosstalk noise exist in thetransmission line, the received singal has poor signal integrity in receiver, which make the designof Serial RapidIO physical layer (PHY) to be difficult.As a part of the PHY, receiver needs highly reliable clock data recovery logic (CDR),whichis more challenging in design.This paper describes the development of the RapidIO interconnect technology andspecification. By analyzing and comparing many kinds of CDR, the paper Selectes aCharge-Pump PLL-based structure combined with our requirements.The chip is designed in full custom, using0.13m CMOS technology with the chip area of0.096mm2.It has been proved that the design of CDR has the high transfer rate up to3.125Gbps.The RMS jitter of CDR is0.13%UI(408.58fs), and the peak to peak jitter of CDR is1%UI(3.32ps). The results show that this design reachs expected target.The main innovation points in this paper can be listed as follows:1. The paper use a programmable switch to control the charge pump circuit,which cansolve some non-ideal effects,such as current mismatch, clock feedthrough and otherissues in the traditional structure;2. The paper proposes a method to generate multiphase clock with lower hardware cost,using a single-ended ring structure. The eight phases clk structure is achieved in form ofMultiple loop nesting with a phase difference of45°;3. A new type of multi-phase clock for Serial to parallel circuit is designed in the paper.Compared with the conventional structure, it is more faster. |
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