Study On Prediction And Optimization Of Parametric Yield Of VLSI IC

This dissertation aims at discussing the prediction and optimization model of parametric yield. The author's main contributions are as follows:A coupling algorithm is proposed based on the centering design and tolerance optimization of parametric yield, which converges to the optimal normal values from given initial design variable and tolerance. In the optimal value, the maximum yield can be obtained according to process condition while proper process conditions can be chosen according to practical requirements.Although the MC based method is applicable to various circuits without simplifying the forms of the probability distribution of parameters and restricting the number of parameters. So it is believed to be the most reliable technique for the statistical analysis of electrical circuits. However, the MC based method requires a large number of circuit simulations to have a valuable estimation. So, a novel yield estimation and optimization method is proposed based on uniform design sampling (UDS) method, which is one kind of Quasi-Monte Carlo method. Compared with primitive statistical methods based on Monte Carlo sampling method, this new method needs only a few circuit simulations to have a valuable estimation and is immune to the number of statistical variables. A comparison of UDS method with the popular Monte Carlo based method-Latin hypercube sampling method is made in this paper to show the efficiency of the new method. Due to that the algorithms available to compute the uniformity of a given point set are complicated and time-consuming, an effective and simple algorithm-k nearest neighbor (ANN) density estimation is introduced to compute the uniformity.Based on the need for method to improve the IC's whole profit, a novel layer yield optimal model is presented in this paper. Firstly, an integrated performance function is formatted. Secondly, According to the integrated performance function, all factors, such as designable parameter, the number of layers and layered parameters are considered together to establish the optimal model. Thirdly a special algorithm is designed for this model with efficiency sampling technology-Uniform Design.The response surface model (RSM) approach establishes a simple relation between input and output of a system without considering its physical essence, theory and process. Utilizing the relation, one can obtain the sensitivity of performance toparameter and the correlation between them. So it is an important way to optimize the process and device. In this paper, a new optimization approach for IC parametric yield is presented, which is based on the RSM and uniform experiment design. Every designable circuit parameter and statistical variation are swept one by one with SPICE in order to determine the variation ranges of these parameters in which the circuit performance meet the special constraints. In above range, a uniform design, which is based on Number Theory, is used to design simulation of circuit to get a precise RSM, which is verified by cross validation method. The optimal parameter will be gotten by an analysis of the RSM.The acceptability is defined in the space of circuit performances. However, the optimize object is the design parameters. How to determine the acceptability region in design space is a difficulty in the optimization of parametric yield. A novel algorithm for global optimization procedure of IC parametric yield is proposed which integrates uniform design searching & mapping distance analysis. Compared with the optimization methods available, it dose not need any calculation of gradient and assumption of initial point. Furthermore, this algorithm has a high convergence rate and is not sensitive to dimension problem.