Hardware And Software Co-design Of Mifare1Reader IC

Mifare1card is widely used in low-end RFID market because of its fasttransaction, stable communication and low cost. Therefore, it is a valuable study thathow to design a reader IC to support Mifare1card. ISO14443A and Mifare1protocoldefines the functions of Mifare1reader IC. According to market application, highspeed, low cost and application scalability are required in the performance of Mifare1reader. In this thesis, a design and implementation of Mifare1reader IC has beengiven to interpret the methodology of IC hardware and software co-design, whichmeans how to obtain an optimal hardware software partition strategy and architectureplan to meet the requirement.After a research of partition basis in IC design, a hardware/software partitionscheme for the functions of Mifare1reader has been presented in this thesis. Theencoder/decoder functions of baseband should be implemented in hardware becauseof its strict timing requirement. Mifare1encryption/decryption functions use hardwareimplementation due to the large amount of computing. However, to ensure theflexibility and scalability, initiation, anti-collision and Mifare1transactions areimplemented in software.An implementation of Mifare1protocol by hardware and software has been shownin this paper after a detailed discussing of Mifare1encryption algorithm. Parallelcomputing is adopted between Mifare1encrypting/decrypting and bitencoding/decoding to shorten the transaction time. And software can flexibly controlhardware through special function registers. In addition, this paper has compared theperformance between this partition scheme and another partition strategyimplementing Mifare1protocol by software only. The result shows that, comparedwith the software only method, the first partition scheme has shortened the transactiontime by47times, reduced the software code size by5times, and is easy to updatingapplication, though the area of hardware has increased by8percent. Consequently, thefirst strategy has a stronger feasibility.Finally, a verification plan has been given. The verification has been done both insimulation and on FPGA. After a successful tape out, the actual test result of the chipis the same as that of simulation and FPGA verification, which shows a successfulmatch with the design goal.The design results have demonstrated the significance of hardware/softwareco-design methodology in IC design. And this reader IC is a good supplement for thehigh speed, low cost RFID market.