Research And Design Of Encryption And Decryption Hardware Accelerator In LTE Terminal

With the rapid development of wireless communication technology, wirelesscommunication has gradually been the main expression and communication in human life.however, a big security risk exists because of the openness of wireless networks. As a verycompetitive wireless access technology, standard of LTE has taken into account security issuesat the very beginning. Whereas, there are limitations for the wireless mobile terminal, such ascalculating ability, storage space, battery capacity, and so on. As a result, some complex dataoperations need to be realized by special hardware accelerator.Based on the AHB bus, a encryption and decryption hardware accelerator used in PDCPlayer of LTE communication terminal has been researched and designed in this thesis. Firstly,the security layer protocol in LTE standard was researched in detail to complete the structuraldesign and module division of the hardware accelerator. Secondly, complete the CCM mode,CTR mode, UIA algorithm, UEA algorithm as well as the hardware design of AES and SNOW3G. During designing the AES core, in order to reduce the hardware area, a special circuitstructure is proposed to realize the ShiftRow operations. According to the composite fieldreduction method, combinational logic circuits are utilized to implement the SubByteoperations. In the design of SNOW3G, AES S-BOX was used by S-BOX S1to save thesources while encryption and integrity protection module were parallel processed to improvethe data processing speed and save resources in the design of encryption and decryption IP. Inthe key management scheme, hardware was used preliminarily in the extended algorithm andsaving of the initial key, what’s more, when the key is unchanged, no extended algorithmshould be performed in the initial key, for which would reduce the power.The hardware accelerator has been described in RTL level using Verilog hardwaredescription language, and EDA was used to analyze the logic function simulation and static timing. Then the whole system was tested by FPGA hardware platform based on Virtex-6. Theresults showed that the speed and resource in the design were balanced on the basis ofachieving the whole functions and the design objective while the design was of high speedarea ratio.