Hardware Design Of Encryption And Decryption Based On AES

The 21st century is the era of information, with the broad application of computer network, the safety of computer network gradually become a focus of attention. It is predictable that the future world would be the era of network and information sharing. So, the safety of network would become more and more important. It is only the safe network that can guarantee the network work orderly, that the network system can't be gone to pot, that information can't be stolen, that the service can't be interrupted. In order to guarantee the safety of network, data that would be transferred should be encrypted by a safe encrypt algorithm.AES(advanced encryption standard)is a encryption standard that was claimed to adopt by National Institute of Standards and Technology, this indicates that AES will play an important role on the field of information safety in a long period in the future. So the research of AES's realization becomes the focus both at home an abroad, and it will be used widely. The realization of AES algorithm has many advantages, such as fast, flexible, has no need for the structure of processor and so on. All of this advantages make realizing AES algorithm with FPGA is a good choice. This text is researching the design and realization of AES algorithm based on FPGA.This text introduced the developing tools, language and chip that has been selected in realizing AES algorithm based on FPGA, and then particularly introduced the realization methods of AES based on hardware, finally provided the whole diagram of the realization of AES algorithm, introduced each part of de design separately and give the timing simulation and result of the design of encryption and decryption.