Hardening Design For External Memory Controller Based On LEON3Processor

Memory of SoC is susceptible to the influence of variety of radiation effects inthe radiation environment. Among them Total Ionizing Dose (TID) and Single EventEffects (SEE) have a dramatic influence on the memory. Total Ionizing Dose effectscause that MOS transistor’s threshold voltage shifts and its leakage current increasesin the memory, resulting in its circuit speed reducing, power consumption increasingor even circuit functional failure. Single Event Effects may make the memory occurhard errors and soft errors. As advanced IC technology developed and feature sizescaled down, Total Ionizing Dose has less effect on memory, but single event upsets(SEU) probability of memory because of Single Event Effects get more and morehigh. Therefore, we can use the error detection and correction (EDAC) techniques toharden the external memory controller (EMC), and improve the capacity of externalmemory against SEU in the design of radiation tolerant SoC.Firstly, the thesis study the encoding and decoding circuit implementationbased on the theory of linear block codes and design two error detection andcorrection circuits using modified Hamming code (39,32) and BCH coderespectively. Modified Hamming code (39,32) can correct one error and detectdouble errors. It is used to design the error detection and correction circuitprotecting the external data of PROM. The error detection and correction circuithardened for SRAM is based on the BCH code. In this thesis, BCH code is theextended code BCH (45,32), and it can correct double errors and detect triple errors.Since the decoding circuit of the Hamming code and BCH code is applied to theexternal memory and needed to adopt parallel decoding algorithm, so the decodingcircuit is complemented by look-up table decoding algorithm that is completed theoperation in one clock cycle.Then, the thesis focuses on complement of error detection and correctioncircuits after design of the codec circuits. Because error detection and correctioncircuit for external PROM is easy to be implemented, the paper focuses on thecomplement of the error detection and correction circuit hardened for the externalSRAM. Error detection and correction circuit for SRAM can execute8,16and32-bit data read and write operations. In addition, it can correct double errors in thedata and re-write the corrected data to avoid the accumulation of soft errors in thememory.Finally, a new external memory controller with error detection and correction functions is complemented with Verilog HDL and is simulated on verificationplatform of SoC based on LEON3processor. The validation results prove theproposed memory controller can work expectedly.