Research On Memory Anti-Single Event Effect Two-Dimensional Code And RS Code

With the development of integrated circuit technology to nano-scale,high density,high performance and low cost,the high frequency and low voltage make it more vulnerable to Single Event Effect in radiation environment,and may cause information loss,system failure and out of control in electronic system.Research shows that soft error is the most important factor affecting integrated circuit compared with hard error in Single Event Effect.Memory relative to combinational logic circuit has always been one of the main considerations of intergrated circuit affected by soft error.In current integrated circuit,there are a large number of memory types such as SRAM,DRAM,NAND Flash,With the progress of integrated circuit technology,the error mode of memory affected by soft error gradually changes from Single Bit Upset to Multiple Bit Upset.Therefore,some measures should be taken to reduce the influence of Single Event Effect on memory,so as to improve the reliability of electronic system in radiation environment.Compared with process-level,circuit level and layout level hardened technology,system level hardened technology represented by Error Correcting Code has higher operational level,does not change the original circuit technology and is easy to implement at lower cost.Traditional system hardened technology usually uses Hamming code as hardened scheme,but with the progress of integrated circuit technology,this code which single error correcting and double error detecting can not satisfied the need of error correction.Therefore,more error-correcting codes need to be corrected as hardened schemes..While guaranteeing that the error correction capability can meet the demand,we should consider the problems of bit rate,actual circuit area,power consumption and delay,seek the balance of performance.A New Two-Dimensional Error Correction Code for SRAM memory is designed as hardened scheme.In principle,one-dimensional information sequence is logically arranged in two-dimensional form.Based on block principle,horizontal parity bits are calculated to detect as many errors as possible,and then corrected by decoding.The simulation results show that the New Two-Dimensional Error Correcting Code has strong error correcting ability and introduce less circuit overhead,it can choose the appropriate construction mode and block length according to the specific application environment,so as to improve the reliability of SRAM by Single Event Effect in radiation environment.And then RS(238,234)+RS(180,176)combination code hardened scheme is designed for NAND Flash memory.This scheme is based on the principle of storing integer digits on pages and placing information bits and parity bits in data storage area and data redundancy area respectively.Itachieves the error correction ability required in NAND Flash by Single Event Effect in radiation environment while satisfying large capacity storage.In order to reduce the critical path delay,the riBM algorithm is used in the Key Equation Solver in decoding steps.Finally,simulation and performance analysis show that the scheme is suitable for harden NAND Flash by Single Event Effect in radiation environment.