Design Of Error Detection And Correction Circuit For New Type Of Non-volatile Memory

With the modern society entering the era of big data and Internet of things,the number of data processed by servers shows a trend of rapid growth,and the semiconductor memory used in modern information technology is also facing new opportunities for diversified development.New types of non-volatile memory(such as MRAM,FRAM,PRAM)are expected to become the dominant direction of memory industry in the future because of their non-volatile characteristics.When a new type of memory is applied to a computer or server,memory bit errors may occur because of the reliability of the memory device,or by an external radiation impact.The error detection and correction circuit is exactly the memory component used in this scenario.As a kind of error correction logic,it is integrated into the internal memory controller,which can effectively correct the soft error phenomenon,thus improve the reliability of the memory and further reduce the probability of computer and server errors.Therefore,it is of great practical significance to study the error detection and correction circuit suitable for the new type of non-volatile memory.Taking the project "Design of LPDDR MRAM Controller" as the carrier,this paper studies the error detection and correction circuit and the principle of error correction code for magnetic memory(MRAM)devices,which mainly includes the following contents:1.a brief introduction is given to several new types of non-volatile random-access memory,including magnetic memory,ferroelectric memory and phase change memory,this paper mainly introduces their historical development process,device structure model,storage principle,excellent characteristics and commercial application prospect.2.analyze the necessity of error detection and correction circuit for memory devices.Then study the error detection and correction circuit based on three kinds of error correction codes,including the principle of these kinds of error correction codes,the encoders and decoders based on Hamming code and BCH code are designed,and their functions are simulated and verified.We also design a parameter template based on Hamming code,which includes the encoder parameter template and the decoder parameter template,the SEC-DED Hamming code error detection and correction circuit can be quickly generated by adjusting only a few of the parameters.3.the key technologies of the MRAM controller are studied,the overall architecture of the controller is planned and designed,and then the sub-functional modules of the controller are designed according to the requirements of the sequence diagram,and then the command processing module,the data processing module and the whole controller are verified.According to the hamming code introduced in this paper,the functional module with error detection and correction circuit is implemented in the MRAM controller,and then its function is verified,thus the data reliability of MRAM memory is enhanced.