Study On The Radiation Hardening Techniques For Mitigating SEU/SET/MBU In MOS Integrated Circuits

With the innovation of IC fabrication process, device scaling and speed increasing, radiation damage due to many different effects is becoming more and more serious. With the introduction of deep submicron MOS device, single event effects (SEE) have become the most important radiation effects for MOS devices, in which SEU, SET and MBU are most remarkable. In order to implement radiation hardening against these effects, MOS circuit hardening in circuit level, layout level and both levels were studied. SRAM and D flip-flop were studied for radiation hardening in circuit level and NMOS transistor was studied for radiation hardening in layout level. SRAM was studied for radiation hardening in both levels.SRAM hardening techniques include DICE, guard-gates and so on. Three radiation hardened SRAM cells were built using DICE, guard-gates and both techniques firstly. They were DICE-SRAM, GG-SRAM and GGDICE-SRAM respectively. SPICE simulation for SEU and MBU tolerance were performed on unhardened SRAM, DICE-SRAM, GG-SRAM and GGDICE-SRAM. Chip area consumptions of hardening techniques were also discussed. The result showed that the SEU critical charge of DICE-SRAM was over 10 times of unhardened SRAM and its area factor was 2. DICE-SRAM was the best choice for radiation hardening only concerns SEU. The SEU critical charge of GGDICE-SRAM was over 10 times of unhardened SRAM and the MBU critical charge of GGDICE-SRAM was over 2.21 times of unhardened SRAM. GGDICE-SRAM’s area factor was 3.5. GGDICE-SRAM was the best choice for radiation hardening concerns both SEU and MBU.D flip-flop hardening techniques include DICE, temporal sampling, guard-gates and so on. Three radiation hardened D flip-flops were also built using DICE, temporal sampling and guard-gates. They were DICEFF, TSFF and GGFF. SPICE simulation for SEU and SET tolerance were performed on unhardened DFF, DICEFF, TSFF and GGFF. Speed and chip area consumptions of hardening techniques were also discussed. The result showed that TSFF and GGFF could withstand SEU charge injection up to 60fC and their input data and clock signal could filter SET pulse with width up to 500ps. Number of MOS transistors for GGFF was 44% of TSFF, and setup time of GGFF was 14% less than TSFF. GGFF was the best choice for SEU and SET hardening.Moreover, Silvaco TCAD mixed-mode simulation was utilized in studying the layout level hardening for NMOS, especially for guard contact optimization. The result showed that the worst case for single event strike was striking into drain of NMOS while biasing drain of NMOS to high and other electrodes to low. LET (radiation dose) must be greater than or equal to 2MeV-cm~2/mg to generate original SET. LET must be greater than or equal to 3MeV-cm~2/mg to generate SET pulse which can propagate effectively in inverter chain without attenuation. Best optimization of well contact was shaping well contact as a closed ring and making that ring as close to MOS device as possible. The SET pulse width generated in hardened NMOS using this method was 63% of the pulse width generated in NMOS which built well contact on one side with the same total well contact’s area as the hardened NMOS.Lastly, Silvaco TCAD mixed-mode simulation was utilized in studying the joint-hardening for SRAM which including DICE technique and ring-shaped well contact. The simulation results showed that the joint-hardened SRAM generated SET with pulse width 37% narrower than DICE-SRAM which only implemented circuit level hardening. And joint-hardened SRAM showed threshold LET at least 50% more than SRAM which only implemented layout level hardening. Joint-hardening was more effective than using only circuit level or layout level hardening techniques in single event effect hardening for SRAM.