Design And Research On Radiation Hardened Smart Power Integrated Circuit

Semiconductor technology plays an extremely important role in aerospace industry.Electronic equipments and systems used in commercial aerospace field need to have adequate reliability and operational life under space radiation environment.These equipments and systems should have enough radiation tolerance.Smart power integrated circuits(SPIC)provide power for all kinds of integrated circuits in equipments and systems,which can be regarded as the "heart" of all integrated circuits and the key components of commercial space equipment.With the development of commercial aerospace industry,the requirement for radiation tolerance of electronic equipments and systems becomes more and stricter.Therefore,the radiation tolerance of SPICs is particularly important,which is the basis for aerospace equipment to work in radiation environment.In European and American countries,the research on radiation hardening has been carried out for decades and achieved good progress in radiation effects and hardening strategies.Several companies in those countries can provide radiation-hardened SPICs and power modules for aerospace use.Domestic research on radiation hardening started relatively late and and there is a big gap with those countries.At present,some progress has been made in discrete radiation-hardened devices,radiation-hardened process,and single event effects hardening for digital circuits.However,the research on hardening technology for SPIC under standard BCD process is still rare.Therefore,the research in this field is of great significance to the commercial aerospace industry.Under this background,this dissertation studies the influence of radiation effects on BJT,MOS,LDMOS and other devices based on standard BCD process.The radiation effects on key analog circuit unit such as voltage pre-regulator,reference and transimpedance amplifier are analyzed.Under the standard BCD process,radiation hardening strategies are proposed and verified for devices and circuits.Based on the research above,a radiation-hardened optical receiver chip for optocoupler and a radiation-hardened Buck DC-DC chip are designed.Specific research contents and main innovations are as follows:1.The mechanism of total ionizing dose(TID)effects in BJT and MOS transistors were studied.The effects of current gain degradation,threshold shift and leakage current increase act on SPIC were analyzed.In order to improve the TID radiation tolerance of the chip,the enclosed layout transistor(ELT)structure was used to harden the MOS transistor.The equivalent aspect ratio(W/L)calculation model of the ELT MOS transistor was studied and verified with Sentaurus simulation tool under 0.18 ?m standard BCD process.In order to design and simulate circuits using ELT MOS,a cell library for ELT MOS devices was created in Cadence.The b-type ELT MOS structure can not achieve small aspect ratio and calculation of aspect ratio is not accurate enough.The maximum deviation of aspect ratio calculation for b-type ELT exceeds 30%.An 8-type ELT structure was proposed,which could make up the deficiency for b-type ELT and controlled the deviation of calculation in less than 6%.2.The TID effects of NMOS power transistor and NLDMOS power transistor were studied.To reduce the TID leakage current effects,the waffle typed layout and athletic track typed layout were proposed respectively under standard BCD process.The results of tape-out and irradiation experiments showed that the TID tolerance of the hardened power transistors was improved to more than 300krad(Si).The relationship between total ionizing dose effects and bias configurations was studied,and the effects of different bias on total dose effect of devices were analyzed.The results were verified by irradiation experiments,which can help to select an appropriate bias conditions in circuit design and irradiation experiments.3.Under standard BCD process,several key circuit units commonly used in radiation hardened SPICs were studied and designed.Based on the radiation effects on BJT transistor,the performance degradation of voltage pre-regulator circuit under radiation was studied.The BJT transistor was replaced by DTMOS,and the ELT MOS device was used to design the radiation hardened voltage pre-regulator circuit.The work principle of voltage reference is similar to that of voltage pre-regulator.DTMOS and ELT MOS device were also used to hardened the voltage reference circuit.The results of tape-out and irradiation experiments showed that the hardened reference voltage shifted maximum of 34 mV at TID of 200krad(Si)and 18 mV at TID of 300krad(Si).A transimpedance amplifier for radiation hardened optocoupler chip was designed.Aiming at the degradation of the responsivity of photodetectors under radiation,a gain self-regulating mechanism was introduced to increase the dynamic input range of transimpedance amplifiers and enhance the TID tolerance of the optocoupler chip.To prevent the possible single event transient effect of the optocoupler chip,a narrow pulse amplitude detector and an adjustable inverter was designed and simulated.4.Under 0.5?m standard BCD process,an optical receiver chip for 10 MBd radiation hardened optocoupler was studied and designed.A radiation hardened current reference circuit for optical receiver chip was designed.The relationship between hysteresis interval,noise and signal amplitude were studied.The minimum signal amplitude and comparator hysteresis interval were determined.A hysteresis comparator for optical receiver chip was designed.In order to improve the radiation tolerance of the optocoupler chip,the hardened transimpedance amplifier with gain self-regulating and the narrow pulse amplitude detector and adjustable inverter circuit designed in this dissertation were used.The ELT MOS device library established in this dissertation was used for harden design and circuit simulation.The chips were fabricated and treated to irradiation experiment.The unhardened chips failed when TID reached 50krad(Si),and the hardened chips still worked normally when TID reached 400krad(Si).5.Under 0.18?m standard BCD process,a radiation hardened Buck DC-DC chip was studied and designed.The valley current mode Buck structure with two N-type power transistors integrated in the chip was selected.The TID radiation harden design of the Buck chip was carried out in aspects of process and devices selection,devices hardening,key circuit units hardening,layout hardening and so on.Finally,the Buck chip was designed to achieve input voltage 6V~15V,output voltage 1.2V,output current 2A,TID tolerance more than 300krad(Si).Sample chips were taped-out after the simulation validation and treated to irradiation experiment.The test results showed that the unhardened chips failed when TID reached 150krad(Si),and the hardened chips still worked normally when TID reached 350krad(Si).