A Research Of Radiation Hardening Of Digital Integrated Circuit In Deep Submicron Technology

With the rapid development of integrated circuit technology,integrated circuits functions are becoming more and more complex.Radiation generated by space and industrial environment will affect semiconductor devices and circuit systems,and may cause the failure of devices and circuit systems.The radiation effects of devices are highly affected attention.In order to ensure the reliability and performance of digital IC in a radiant environment,it is necessary to continuously develop radiation hardening technology.In the field of micron and nanoscale semiconductors,the single-event effect has become one of the most concerned reliability issues in digital devices.In this paper,based on the pulse laser research platform,SEE simulation was carried out on the shift register circuit in 28-nm double-well and triple-well technology,and the single-event transient effects of the triple-well?deep n-well?structure in 130nm process were analyzed using3D TCAD simulation software.Several measures to harden the triple-well device to suppress the parasitic bipolar amplification effect were simulated and verified,including:1.Based on the 28nm process,a shift register chain was designed and used to replace the SRAM memory for the SEE test.By setting a control group,the results show that the triple-well process compared with the double-well will cause the SEU threshold to decrease,and the soft error rate increases.2.Three-dimensional TCAD device simulation was used to simulate the SET effect of NMOS in a 130-nm triple-well technology.By observing the corresponding SET with heavy ion incidence with different linear energy transfer,the study found that the triple-well NMOS has a significant parasitic bipolar amplification effect.The study found that DNW with a higher doping concentration and a smaller depth enhances the parasitic bipolar amplification effect.Studies have found that the particles striking the drain of the device and the incident direction toward the source have the strongest parasitic effect and SET.The results show that adding a deep n-well to the PMOS reduces the resistance of the PMOS well,thereby obtaining a certain hardening effect.3.Radiation simulation shows that increasing the contact area of the p-well can reduce parasitic effects and SET compared to adjusting the well contact position,plus positive bias at the source compared to negative bias at the substrate.Increasing the doping concentration of the well,and the charge collection of the drain can be reduced.An effective P+strip doping technique is discussed.The results show that the single pulse transient pulse width is reduced by about 56%and the charge collection is reduced by about 61% after hardening.In this paper,a total ionizing dose irradiation experiment with a dose of about2Mrad?Si?was performed on a 28nm bulk NMOS device using a ⁶⁰Co-?ray source.The results showes that the degradation including the threshold voltage V_TH,the on current I_on,and the sub-threshold swing is very small.Threshold voltage drift and STI sidewall charge increase the cut-off leakage current by two orders of magnitude,and the gate current growth trend is consistent with the fixed trap of the oxide and the threshold voltage drift.