Hardware Design Of Dual-mode Entropy Decoder In AVS And H.264

In order to meet the needs of the development of multimedia communications, the International Telecommunication Union and the Moving Picture Experts Group have developed a new generation video compression standard H.264/AVC. Because of its excellent compression performance and network adaptability, H.264is now considered the most influential industry standard. AVS is the second generation source coding standard with independent intellectual property rights of China, and it is popularized by our country now. In the future the two standards will integrate and develop with each other, so the design of dual-mode entropy decoder for AVS and H.264is very meaningful.This paper first studies the standards of AVS and H.264and compares their similarities and differences, and then analyzes their entropy coding algorithm. After that, we propose the hardware structure of the dual-mode entropy decoder. The structure supports CA-2D-VLC decoding of AVS, CAVLC decoding and CABAC decoding of H.264. The reuse of barrel shifter and exp-colomb decoder is adopted to save hardware resources. We optimize and rebuild code tables of AVS and H.264to reduce the complexity of code tables and improve the efficiency of table index. We use pipeline structure to improve decoding speed. The decoder uses combinational logic to look up table in order to avoid the access to memory. CAVLC decoding module decodes Coffetoken and T1in one clock and it rebuilds residual blocks when decoding Runbefore. This paper propose efficient CABAC decoding structure. The CABAC decoding module uses dual-port RAM to save and read context models and it has fast arithmetic decoding module to improve CABAC decoding speed.This paper has finished RTL design of the dual-mode entropy decoder by Verilog HDL. We also write C reference model of the decoder according to RM52j reference software and JM9.4reference software. We carry out functional simulation for the design by VCS and compare the results with the output of C reference model to verify the correctness of the design. Using TSMC0.13um technology library, we synthesize the RTL design by Design Compiler tool. The synthesis results show that the decoder can work at77MHz clock frequency to meet the real-time decoding requirement of4CIF and720p HD video. At last we finsh formal verification by Formality tool after synthesis.The verification and synthesis results indicate that the design of dual-mode entropy decoder has achieved design objective.