Design And Implementation Of High Speed Data Transmission System Base On Pciexpress

With the growing demand of bandwidth for computer application, PCI Express bus specification, as the Third Gneration Input/Output standard, own many advantages such as point to point transimission and serial data stream which makes it become the trend in bus technology field.The high speed data transmission system refers to the DNS firewall device which implements the communication between the upper server host and lower hardware board through the PCI Express bridge chip. The first part describes the basic principle of PCI Express bus protocol. The second part gives the overview on the DNS device which consists of the hardware, software and web application. The last part presents the design and implementation of the PCI Express bridge chip based on FPGA.The FPGA of Altera Cyclon IV GX family chip, embed with PCIe IP core. The hard IP core implements the functions of transaction layer, data link layer and physical layer. So the subject needs to implement the logic design on PCIe application layer. The application layer is designed to implement programming input/output transmission and DMA transmission.The subject makes a demand analysis on high speed data transmission system, then gives design scheme of PCI Express bridge chip, including logic design block diagram, interface description and bus timing. On the basis of scheme, the RTL coding is used in Verilog HDL language to implement PIO transmission and DMA transmission. In the end, the simulaiton of high speed data transmission system shows that DMA read data rate is168MB/s, DMA write data rate is172MB/s. So the design meets the requirements of high speed rate between upper server host and lower hardware board. In addition, we can expand the design by using X4channel to get higher speed rate. Now, the DNS firewall is deployed and used successfully.