Design And Implementation Of Phy Layer Hardware In10G Wdm-Epon Suppoerting Symmetric10GIT/S

With the development of the Internet, more and more network services are needed. Access network bandwidth demand has increased dramatically. WDM PON is one of the main solutions of next generation access network. Nowadays, WDM PON is still in the research stage and still has quite a long distance away from practical. There remain some key issues to be solved in the WDM PON:AWG performance is affected greatly by environment factors, the technology of "colorless" light source isn’t mature, the handling for lOGbps baseband signal isn’t clear, the upstream bandwidth is becoming unsufficient and there is no unified international standard of WDM PON.Based on the study on EPON and WDM PON system, this subject proposes a hardware design of WDM-EPON system which supports symmetric10.0Gbit/s network. The WDM-EPON system uses a RSOA to modulate the10G serial data directly. In addition, we use FPGA to encode the signal by FEC for lower rate error and better transmission performance. The encode signal will be in16road and622Mbps low rate, the output interface is XSBI. In order to connect the interface XFI, we design a mux/demux functional board which achieves the transformation between lOGbps high-speed signals and622Mbps low-speed signals. We use the10G-SerDes as the core chip to transmit and receive the lOGbps serial data. It is the focus and difficulty of the system PHY layer hardware design.This paper describes the architecture of10G WDM-EPON system and designs the hardware platform of10G WDM-EPON system. Based on the hardware design theory of high-speed circuit, this paper analysis the high speed signal integrity in PCB and design the mux/demux functional board, which is used to connect XSBI interface and XFI interface. The functional board mainly includes lOG-SerDes transceiver module, clock module, control module and power module. Finally, we test the mux/demux functional board.